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VHDL/FPGA/Verilog Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation.
As with the SPI found in MC68HC11 processo ...
串口编程 uart协议、实现、验证
uart协议、实现、验证，基于wishbone协议，工业标准为16550A
USB编程 USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.
USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Supports the four types of USB data transfer control, bulk, interrupt, and isochronous
transfers.
– Host ...
VHDL/FPGA/Verilog This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.
The core acts as a slave WISHBONE device.
The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an u ...
源码 LPC master verilog source（内附LPC标准协议文档）
用户接口Wishbone bus 接口，
驱动LPC master去主动访问 slave 寄存器表（地址可更改）
读取到寄存器封装到用户层
可按要求更改设计
技术资料 Altium Designer 09 中文版软件下载，附破解安装教程
Altium Designer Summer 09的发布延续了连续不断的新特性和新技术的应用过程。这必将帮助用户更轻松地创建下一代电子设计。同时，我们将令Altium Designer更符合电子设计师的要求。Altium的一体化设计结构将硬件、软件和可编程硬件集合在一个单一的环境中，这将令用户自由地探索新的设计构想。在整个设计构成中，每个人都使 ...
VIP专区 VIP专区-嵌入式/单片机编程源码精选合集系列（126）
VIP专区-嵌入式/单片机编程源码精选合集系列（126）资源包含以下内容：1. 嵌入式开发讲义.2. can总线部分的基本应用.3. sysinternals公司的文件系统监视工具源代码.4. c8051f的控制直流电动机的源程序.5. proteus仿真LIUSHUIDENG的例子.6. YM12864液晶模块的驱动程序.7. 本课题要求在研究PC机键盘通信协议的基础上.8. 在FPG ...