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其他  Full adder using Verilog

Full adder using Verilog

https://www.eeworm.com/dl/534/331453.html

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其他行业  Computtional Fluid Dynamics (CFD) steady 1-Dimensional convection and diffusion using central diff

Computtional Fluid Dynamics (CFD) steady 1-Dimensional convection and diffusion using central differencing, upwind differencing, hybrid differencing and power law schemes, programmed in MATLAB

https://www.eeworm.com/dl/668/331480.html

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其他  SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU,

SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Go ...

https://www.eeworm.com/dl/534/331886.html

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SQL Server using java jdbc-odbce brige to Connect SQL2

using java jdbc-odbce brige to Connect SQL2

https://www.eeworm.com/dl/689/331903.html

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matlab例程  The Finite Element Method Using MATLAB

The Finite Element Method Using MATLAB

https://www.eeworm.com/dl/665/331961.html

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单片机开发  keypad controlling using PIC16F877 by C

keypad controlling using PIC16F877 by C

https://www.eeworm.com/dl/648/333820.html

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单片机开发  USB CDC using C8051F320/340, virtual COM port thru usb connection

USB CDC using C8051F320/340, virtual COM port thru usb connection

https://www.eeworm.com/dl/648/334134.html

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Java编程  Laser Control is a java program that using a webcam detects when a laser pointer is in a specified h

Laser Control is a java program that using a webcam detects when a laser pointer is in a specified hotspot and then does the equivalent of pressing a specified keyboard key. thus controlling Media Portal through it s hot keys. the hotspots can be set by the user as well as the actions taken. Make yo ...

https://www.eeworm.com/dl/633/335374.html

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VHDL/FPGA/Verilog For developers using FPGAs for the implementation of floating-point DSP functions, one key challen

For developers using FPGAs for the implementation of floating-point DSP functions, one key challenge is how to decompose the computation algorithm into sequences of parallel hardware processes while efficiently managing data flow through the parallel pipelines of these processes.

https://www.eeworm.com/dl/663/335858.html

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书籍源码  This is Visual C++ basis operation. Using that you can fast go in study.

This is Visual C++ basis operation. Using that you can fast go in study.

https://www.eeworm.com/dl/532/336101.html

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