搜索结果

找到约 1,279 项符合 Two-input 的查询结果

数值算法/人工智能 Muscl Euler Two dimensions

Muscl Euler Two dimensions
https://www.eeworm.com/dl/518/383616.html
下载: 156
查看: 1034

系统设计方案 measure through the cross-entropy of test data. In addition, we introduce two novel smoothing tech

measure through the cross-entropy of test data. In addition, we introduce two novel smoothing techniques, one a variation of Jelinek-Mercer smoothing and one a very simple linear interpolation technique, both of which outperform existing methods.
https://www.eeworm.com/dl/678/383814.html
下载: 179
查看: 1028

matlab例程 Train a two layer neural network with a recursive prediction error % algorithm ("recursive Gauss-Ne

Train a two layer neural network with a recursive prediction error % algorithm ("recursive Gauss-Newton"). Also pruned (i.e., not fully % connected) networks can be trained. % % The activation functions can either be linear or tanh. The network % architecture is defined by the matrix NetDef , w ...
https://www.eeworm.com/dl/665/384109.html
下载: 78
查看: 1074

matlab例程 数值计算牛顿迭代法的matlab源程序 说明如下: %fun----input,the part as the form of f(x) in the equation f(x)=0 % ini

数值计算牛顿迭代法的matlab源程序 说明如下: %fun----input,the part as the form of f(x) in the equation f(x)=0 % ini----input,sets the starting point to ini % err----input,sets admissible error % sol----output,returns the root of equation
https://www.eeworm.com/dl/665/386284.html
下载: 91
查看: 1055

数学计算 数值分析高斯——列主元消去法主程序 说明如下: % a----input,matrix of coefficient % b----input,right vector % sol----o

数值分析高斯——列主元消去法主程序 说明如下: % a----input,matrix of coefficient % b----input,right vector % sol----output,returns the solution of linear equation
https://www.eeworm.com/dl/641/386288.html
下载: 29
查看: 1101

VHDL/FPGA/Verilog verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input

verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0
https://www.eeworm.com/dl/663/388874.html
下载: 147
查看: 1126

VHDL/FPGA/Verilog verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y

verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y
https://www.eeworm.com/dl/663/388881.html
下载: 89
查看: 1053

VHDL/FPGA/Verilog verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient

verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient output [8:0]Remainder
https://www.eeworm.com/dl/663/388882.html
下载: 147
查看: 1085

数学计算 This program produces a Frequency Domain display from the Time Domain * data input using the Fast

This program produces a Frequency Domain display from the Time Domain * data input using the Fast Fourier Transform.
https://www.eeworm.com/dl/641/390402.html
下载: 50
查看: 1051

加密解密 This work briefly explains common cryptosystems and details two most popular private-key ciphers: DE

This work briefly explains common cryptosystems and details two most popular private-key ciphers: DES ,which is probably the most widely used, and AES, which is intended to replace DES.
https://www.eeworm.com/dl/519/391402.html
下载: 194
查看: 1041