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其他 Two-Dimensional PCA: A New Approach to Appearance-Based Face Representation and Recognition
Two-Dimensional PCA:
A New Approach to Appearance-Based
Face Representation and Recognition
单片机开发 T9 Text Input You can use this source code for input T9 Text Input(English)
T9 Text Input
You can use this source code for input T9 Text Input(English)
软件设计/软件工程 Here are two newest published articles talking about joint source channel coding, in which source co
Here are two newest published articles talking about joint source channel coding, in which source coding is invovled scalable video coding. They are very useful for people who are doing research about it.
matlab例程 外国人开发的电磁时域有限差分方法工具包 Electromagnetic Finite-Difference Time-Domain (EmFDTD) is a basic two-dimensio
外国人开发的电磁时域有限差分方法工具包
Electromagnetic Finite-Difference Time-Domain (EmFDTD)
is a basic two-dimensional FDTD code developed at the
School of Electrical Engineering, Sharif University of
Technology.
This code has been written based on the standard
Yee s FDTD algorithm. Applicati ...
文章/文档 The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general co
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control
and data transfer communication between ICs.
Some of the features of the I2C bus are:
&#8226 Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A
...
单片机开发 input code control please see
input code control please see
单片机开发 TL062/TL064 MOTOROLA开发的low power JFET input operational amplifiers
TL062/TL064 MOTOROLA开发的low power JFET input operational amplifiers
其他 simulating a convolutional encoder allows the user to input a source code to be encoded and also in
simulating a convolutional encoder
allows the user to input a source code to be encoded and also input the values of the generator polynomials. It outputs the encoded data bits, where 1/n is the code rate
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...