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其他 This m file simulates a differential phase shift keyed (DPSK) ultra wide bandwidth(UWB) system using

This m file simulates a differential phase shift keyed (DPSK) ultra wide bandwidth(UWB) system using a fifth derivative waveform equation of a Gaussian pulse.
https://www.eeworm.com/dl/534/365760.html
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单片机开发 The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a

The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry. The 3-S ...
https://www.eeworm.com/dl/648/369026.html
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压缩解压 Range imaging offers an inexpensive and accurate means for digitizing the shape of three-dimensiona

Range imaging offers an inexpensive and accurate means for digitizing the shape of three-dimensional objects. Because most objects self occlude, no single range image suffices to describe the entire object. We present a method for combining a collection of range images into a single polygonal mesh t ...
https://www.eeworm.com/dl/617/372623.html
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matlab例程 script for generting transmit waveforms in a minimum shift keying, a form of continuous phase freque

script for generting transmit waveforms in a minimum shift keying, a form of continuous phase frequency shift keying
https://www.eeworm.com/dl/665/373209.html
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编译器/解释器 This program is about Compilers.A source routine that need to be compiled need process three section

This program is about Compilers.A source routine that need to be compiled need process three sections.It is about the third section.
https://www.eeworm.com/dl/628/373463.html
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VHDL/FPGA/Verilog ADPLL of high level phase locked loop

ADPLL of high level phase locked loop
https://www.eeworm.com/dl/663/374918.html
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其他 A high-speed variable phase accumulator for an ADPLL architecture

A high-speed variable phase accumulator for an ADPLL architecture
https://www.eeworm.com/dl/534/374925.html
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其他 A Top-Down Verilog-A Design on the digital phase-lockedmloop

A Top-Down Verilog-A Design on the digital phase-lockedmloop
https://www.eeworm.com/dl/534/374926.html
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其他 A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops

A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops
https://www.eeworm.com/dl/534/374927.html
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文件格式 Ethernet Services Attributes Phase

Ethernet Services Attributes Phase
https://www.eeworm.com/dl/639/375392.html
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