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可编程逻辑 WP151 - Xilinx FPGA的System ACE配置解决方案

Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bo ...
https://www.eeworm.com/dl/kbcluoji/40068.html
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可编程逻辑 Virtex-6 FPGA PCB设计手册

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in ...
https://www.eeworm.com/dl/kbcluoji/40076.html
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可编程逻辑 WP264-在数字视频应用中使用CPLD

  The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blo ...
https://www.eeworm.com/dl/kbcluoji/40077.html
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可编程逻辑 WP196-平面显示器中的Xilinx器件

  According to CIBC World Markets, Equity Research, theFlat Panel Display (FPD) industry has achieved sufficientcritical mass for its growth to explode. Thus, it can nowattract the right blend of capital investments and R&Dresources to drive technical innovation toward continuousimprovement ...
https://www.eeworm.com/dl/kbcluoji/40083.html
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可编程逻辑 XAPP740利用AXI互联设计高性能视频系统

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizat ...
https://www.eeworm.com/dl/kbcluoji/40103.html
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可编程逻辑 XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接  The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and ...
https://www.eeworm.com/dl/kbcluoji/40104.html
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可编程逻辑 XAPP483 - 利用 Platform Flash PROM 实现多重启动功能

  一些应用利用 Xilinx FPGA 在每次启动时可改变配置的能力,根据所需来改变 FPGA 的功能。Xilinx Platform Flash XCFxxP PROM 的设计修订 (Design Revisioning) 功能,允许用户在单个PROM 中将多种配置存储为不同的修订版本,从而简化了 FPGA 配置更改。在 FPGA 内部加入少量的逻辑,用户就能在 PROM 中存储的多 ...
https://www.eeworm.com/dl/kbcluoji/40116.html
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可编程逻辑 WP369可扩展式处理平台-各种嵌入式系统的理想解决方案

WP369可扩展式处理平台-各种嵌入式系统的理想解决方案 :Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-c ...
https://www.eeworm.com/dl/kbcluoji/40117.html
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可编程逻辑 WP253 - 简化FPGA配置设计过程

  本文着重介绍了 Xilinx Platform Flash PROM 如何帮助系统和电路板设计人员简化 FPGA 配置设计。用于配置 FPGA 的可选解决方案有很多,但它们通常都需要大量的前期设计工作和时间。Platform Flash 是为配置 Xilinx FPGA 专门设计的一款包括硬件和软件支持在内的整体解决方案。 ...
https://www.eeworm.com/dl/kbcluoji/40126.html
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可编程逻辑 FPGA设计重利用方法(Design Reuse Methodology)

  FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many a ...
https://www.eeworm.com/dl/kbcluoji/40133.html
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