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其他 Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
单片机开发 时间片系统time slicing system
时间片系统time slicing system ，基于PICDEM 2 PLUS开发板pic16f877a芯片上的代码。
单片机开发 The ISD51_Demo project for the MSC1200 shows how to use the ISD51 In-System-Debugger with flash bre
The ISD51_Demo project for the MSC1200 shows how to use the ISD51
In-System-Debugger with flash breakpoints or hardware breakpoints.
By default, it is configured for flash breakpoints which allow you
to set real-time breakpoints in your software. Using Flash breakpoints
has also the benefit that no ...
VxWorks About communication in Vxworks system
About communication in Vxworks system
VHDL/FPGA/Verilog ADPLL of high level phase locked loop
ADPLL of high level phase locked loop
SQL Server 图书馆管理系统 library control system
图书馆管理系统
library control system
网络 monitor the local system resource
monitor the local system resource
Linux/Unix编程 embeded operation system
embeded operation system
其他书籍 The System Management BIOS Reference Specification addresses how motherboard and system vendors pres
The System Management BIOS Reference Specification addresses how motherboard and system vendors present
management information about their products in a standard format by extending the BIOS interface on Intel
architecture systems. The information is intended to allow generic instrumentation to deli ...
VHDL/FPGA/Verilog SoC-Wishbone System IP核的VHDL语言源代码
SoC-Wishbone System IP核的VHDL语言源代码