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matlab例程 Some algorithms of variable step size LMS adaptive filtering are studied．The VS—LMS algorithm is imp
Some algorithms of variable step size LMS adaptive filtering are studied．The VS—LMS algorithm is improved．
Another new non-linear function between肛and e(／ t)is established．The theoretic analysis and computer
simulation results show that this algorithm converges more quickly than the origina1． ...
技术资料 51单片机TLC2543电压表相关资料
说明： 基于51单片机的数字直流电压表相关材料，内容有原理图，仿真文件，论文材料，程序源码等。(The related materials of digital DC voltmeter based on 51 single chip computer include schematic simulation files, paper materials, program source code, etc.)
allegro Verilog编码中的非阻塞性赋值
 
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...
可编程逻辑 Verilog编码中的非阻塞性赋值
 
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...
其他 TOYFDTD1 is a stripped-down minimalist, 3D FDTD code demonstrating the basic tasks in implementing a
TOYFDTD1 is a stripped-down minimalist, 3D FDTD code demonstrating the basic tasks in implementing a simple 3D FDTD simulation. An idealized rectangular waveguide is modeled by treating the interior of the mesh as free space and enforcing PEC conditions on the faces of the mesh. A simplified plane w ...
微处理器开发 The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and ...
其他 The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) d
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip
(SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent
method for simulation and synthesis. The library is vendor independent, with support for different
CAD tools and ta ...
通讯/手机编程 Computes BER v EbNo curve for convolutional encoding / soft decision Viterbi decoding scheme assum
Computes BER v EbNo curve for convolutional encoding / soft decision
Viterbi decoding scheme assuming BPSK.
Brute force Monte Carlo approach is unsatisfactory (takes too long)
to find the BER curve.
The computation uses a quasi-analytic (QA) technique that relies on the
estimation (approximate on ...
单片机开发 Many CAD users dismiss schematic capture as a necessary evil in the process of creating PCB layout
Many CAD users dismiss schematic capture as a necessary evil in the process of creating
PCB layout but we have always disputed this point of view. With PCB layout now offering
automation of both component placement and track routing, getting the design into the
computer can often be the most time co ...
matlab例程 MATSNL is a package of MATLAB M-files for computing wireless sensor node lifetime/power budget and
MATSNL is a package of MATLAB M-files for computing wireless sensor node
lifetime/power budget and solving optimal node architecture choice problems. It is intended
as an analysis and simulation tool for researchers and educators that are easy to use and
modify. MATSNL is designed to give the rough ...