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可编程逻辑  XAPP694-从配置PROM读取用户数据

This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in t ...

https://www.eeworm.com/dl/kbcluoji/40049.html

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可编程逻辑  XAPP228 -Virtex器件内的四端口存储器

This application note describes how the existing dual-port block memories in the Spartan&trade;-IIand Virtex&trade; families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in ...

https://www.eeworm.com/dl/kbcluoji/40055.html

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可编程逻辑  XAPP444 - CPLD配件,技巧和窍门

Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determ ...

https://www.eeworm.com/dl/kbcluoji/40063.html

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可编程逻辑  基于CPLD的QDPSK调制解调电路设计

为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中 ...

https://www.eeworm.com/dl/kbcluoji/40237.html

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可编程逻辑  PCB设计问题集锦

PCB设计问题集锦问：PCB图中各种字符往往容易叠加在一起，或者相距很近，当板子布得很密时，情况更加严重。当我用Verify Design进行检查时，会产生错误，但这种错误可以忽略。往往这种错误很多，有几百个，将其他更重要的错误淹没了，如何使Verify Design会略掉这种错误，或者在众多的错误中快速找到重要的错误。　　　答 ...

https://www.eeworm.com/dl/kbcluoji/40440.html

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可编程逻辑  pci e PCB设计规范

This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on b ...

https://www.eeworm.com/dl/kbcluoji/40445.html

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测试测量  XAPP713 -Virtex-4 RocketIO误码率测试器

&nbsp; The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in t ...

https://www.eeworm.com/dl/544/41859.html

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Internet/网络编程  ngrep strives to provide most of GNU grep s common features, applying them to the network layer. ngr

ngrep strives to provide most of GNU grep s common features, applying them to the network layer. ngrep is a pcap-aware tool that will allow you to specify extended regular or hexadecimal expressions to match against data payloads of packets. It currently recognizes TCP, UDP and ICMP across Ethernet, ...

https://www.eeworm.com/dl/620/107060.html

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uCOS 介绍几种cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducin

介绍几种cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the 8xC251SA/SB/SP/SQ microcont ...

https://www.eeworm.com/dl/649/128798.html

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Java书籍  Invoke JavaProg.main() from a win32 program: . compile Main.java . compile VC project . set include

Invoke JavaProg.main() from a win32 program: . compile Main.java . compile VC project . set include path for jni.h, which is under java_Home\include . set linking path for jvm.lib, which is under java_Home\lib\jvm.lib . copy Main.class and Main$1.class to the working dir of the VC project (or the sa ...

https://www.eeworm.com/dl/656/135351.html

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