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VHDL/FPGA/Verilog Xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”
Xilinx is disclosing this Specification
? 第 1 章“EMIF 概述”，概述 Texas Instruments EMIF。
? 第 2 章“Virtex-II 系列或 Spartan-3 FPGA 到 EMIF 的设计”描述将 TI TMSC6000
EMIF 连接到 Virtex?-II 系列或 Spartan?-3 FPGA 的实现。
? 第 3 章“Virtex-4 FPGA 到 EMIF 的设计” 描述将 TI TMS320C64x EMIF 连接 ...
VHDL/FPGA/Verilog It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spa
It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.
VHDL/FPGA/Verilog Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of
Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of
the Xilinx\Digilent Spartan-3 demo board.
其他书籍 This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware
This paper shows the development of a 1024-point
radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx庐 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit da ...
VHDL/FPGA/Verilog Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i
Working RS232 controller running at 9600 Hz.
Consist of Transmitter and Receiver Module.
Tested in FPGA Spartan 3
Included files for testing at FPGA
- Scan4digit .vhd - to display at 7 sgement display
- D4to7 .vhd - Convert HEX decimal to ASCII code.
VHDL/FPGA/Verilog FPGA 并行NOR FLash的操作相关
FPGA 并行NOR FLash的操作相关，很实用的，基于Xilinx SPartan-3
手册 Xilinx 主流芯片选型指导
Xilinx 主流芯片选型指导,主要讲述了Spartan系列和vertex系列的优缺点和选用偏好
书籍 Spartan-6用户手册
XILINX的sp6实用手册，自己看吧，挺不错的！！！！！
技术资料 Xilinx Spartan 6的DDR3原理图+用户手册
板子采用4层PCB，层叠情况：Top -> GND -> Power -> Bottom板子芯片情况：(1) FPGA: Xilinx Spartan6系列的XC6SLX16-FTG256(2) DDR3: Micron的MT41J128M16，2Gbit存储容量(2) 电源：采用2片Onsemi的NCP1529分别为FPGA Core 1.2V和DDR3 1.5V提供电源FPGA的1.2V VDDCore电压，1.5V的DDR3供电电压，VREF的0.75V电压都OK。往FPG ...
技术资料 微弱信号检测与辨识机制研究
微弱信号检测的目的是从噪声中提取有用信号，或用一些新技术和新方法来提高检测系统输出信号的信噪比。本文简要分析了常用的微弱信号检测理论，对小波变换的微弱信号检测原理进行了进一步的分析。然后提出了微弱信号检测系统的软硬件设计，在阐述了系统的整体设计的基础上，对电路所选芯片的结构和性能进行了简单的介绍，选 ...