搜索结果
找到约 503 项符合
SPA-BUS 的查询结果
DSP编程 Bootloading the TMS320VC5506/C5507/C5509 A digital signal processor (DSP) through the on-chip unive
Bootloading the TMS320VC5506/C5507/C5509 A digital signal processor (DSP)
through the on-chip universal serial bus (USB) peripheral is part of the standard
bootloader provided on the device. This document describes the procedures for
physically connecting the DSP to a USB host, invoking the USB boot ...
系统设计方案 开发sd卡应用所必须的文档
开发sd卡应用所必须的文档,很重要哦。
sd卡有 bus模式和spi模式两种。
Windows CE pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM92
pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by
Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture
with separate 16KB instruction and 16KB data caches, each with an 8-word ...
编译器/解释器 this is a stepper motor controller with specifications pins: for RS-232 interfacing stepper motor:
this is a stepper motor controller with specifications pins: for RS-232 interfacing
stepper motor: 47-50 bus
PUSH button: 9-15
POTEN:9-15
数学计算 observable distribution grid are investigated. A distribution grid is observable if the state of th
observable distribution grid are investigated. A distribution
grid is observable if the state of the grid can be fully determined.
For the simulations, the modified 34-bus IEEE test feeder is used.
The measurements needed for the state estimation are generated
by the ladder iterative technique. Two ...
VHDL/FPGA/Verilog It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spa
It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.
微处理器开发 200-MHz ARM920T Processor • 16-kbyte Instruction Cache • 16-kbyte Data Cache •
200-MHz ARM920T Processor
&#8226 16-kbyte Instruction Cache
&#8226 16-kbyte Data Cache
&#8226 Linux&reg , Microsoft&reg Windows&reg CE-enabled MMU
&#8226 100-MHz System Bus
&#8226 MaverickCrunch&#8482 Math Engine
&#8226 Floating Point, Integer, and Signal Processing
Instructions
&#8226 Opt ...
系统设计方案 The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memor
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device鈥檚
cascadable feature allows up to four devices to share a common two-wire bus. The
device is optimized for use in many industrial and c ...
其他书籍 The main MIPS processor of SMP8630 comes with a JTAG interface, allowing: access to caches and da
The main MIPS processor of SMP8630 comes with a JTAG interface, allowing:
access to caches and data bus (DRAM) with a bandwidth of about 200kbit/s
examining the processor state whatever the execution mode (monice)
connecting to monice using mdi-server and using a gdb client on the processor to st ...
USB编程 USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.
USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Supports the four types of USB data transfer control, bulk, interrupt, and isochronous
transfers.
– Host ...