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ARM LPC1850 Cortex-M3内核微控制器数据手册
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU ...
ARM LPC4300系列ARM双核微控制器产品数据手册
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU ...
ARM LPC315x系列ARM微控制器用户手册
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, in ...
可编程逻辑 Xilinx UltraScale：新一代架构满足您的新一代架构需求（EN）
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class ...
可编程逻辑 AXI总线功能模块v1.1产品简介（英文资料）
AXI Bus Functional Model v1.1 Product Brief.pdf
可编程逻辑 IPC-SM-782
Altium Designer Winter09 最新PCB库，也是最全的。
可编程逻辑 XAPP122 - Spartan-XL FPGA的Express配置
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express con ...
可编程逻辑 PLB Block RAM(BRAM)接口控制器
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
可编程逻辑 XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥
 
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Spec ...
工控技术 can-bus规范2.0版本
随着串行通讯进入更多应用领域，因此，在一些应用里，需要对通讯功能的报文识别位提出分配标准化的要求。原先的地址范围由 11 个识别位定义，如果地址范围扩大，则这些应用就可以更好地由 CAN 来实现。因此引入了第二种报文格式（‘扩展格式’）的概念，其定义的地址范围更宽，由 29 位定义。 ...