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VHDL/FPGA/Verilog VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register betw
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- s ...
编译器/解释器 this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 compu
this a pack include source code for quartus 2.
It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 ...
软件工程 ARMask.The ARM has six operating modes: • User (unprivileged mode under which most tasks run)
ARMask.The ARM has six operating modes:
&#8226 User (unprivileged mode under which most tasks run)
&#8226 FIQ (entered when a high priority (fast) interrupt is raised)
&#8226 IRQ (entered when a low priority (normal) interrupt is raised)
&#8226 Supervisor (entered on reset and when a Software Interr ...
文章/文档 This document is an operation guide for the MPC8XXFADS board. It contains operational, functional a
This document is an operation guide for the MPC8XXFADS board. It contains operational, functional
and general information about the FADS. The MPC8XXFADS is meant to serve as a platform for s/
w and h/w development around the MPC8XX family processors. Using its on-board resources and its
associated d ...
单片机开发 Device pins that are not connected to a specific peripheral function are controlled by the GPIO reg
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simu
中文
单片机开发 The ISD51_Demo project for the MSC1200 shows how to use the ISD51 In-System-Debugger with flash bre
The ISD51_Demo project for the MSC1200 shows how to use the ISD51
In-System-Debugger with flash breakpoints or hardware breakpoints.
By default, it is configured for flash breakpoints which allow you
to set real-time breakpoints in your software. Using Flash breakpoints
has also the benefit that no ...
VHDL/FPGA/Verilog The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA i
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until ...
串口编程 Can通讯的源码
Can通讯的源码，Defines the special registers and firmware programs for lpc22xx\lpc212x\lpc211x\lpc210x
其他书籍 Builder uses to integrate a larger system module. Each component consists of a structured set of fi
Builder uses to integrate a larger system module. Each component
consists of a structured set of files within a directory.
The files in a component directory serve the following
The RS232 UART Core implements a method for communication of serial data. The core provides
a simple register-mapped Avalo ...
汇编语言 This program implements a PIC-based fuzzy inference engine for the Fudge fuzzy development system
This program implements a PIC-based fuzzy inference engine for the Fudge fuzzy development system from Motorola.
It works by taking the output from Fudge for the 68HC11 processor, and converting it to a MPASM compatible assembler file using the convert
batch file.
This file can then be incorp ...