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其他 The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services.
The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services. SEDA has three major goals:
To support massive concurrency, on the order of tens of thousands of clients per node
To exhibit robust performance under wide variations in load and,
To simplify the ...
压缩解压 QccPackSPIHT-0.54-1 (release 2007-04-30) The Set Partitioning in Hierarchical Trees (SPIHT) algorit
QccPackSPIHT-0.54-1 (release 2007-04-30)
The Set Partitioning in Hierarchical Trees (SPIHT) algorithm for wavelet-based image coding .
压缩解压 QccPackSPECK-0.54-1 (release 2007-04-30) is The Set-Partitioning Embedded Block (SPECK) algorithm fo
QccPackSPECK-0.54-1 (release 2007-04-30) is The Set-Partitioning Embedded Block (SPECK) algorithm for wavelet-based image coding.
matlab例程 Demonstrates 1-D FDTD initial state formation. Please edit the FLAGS for demonstration of different
Demonstrates 1-D FDTD initial state formation. Please edit the FLAGS for demonstration of different cases. BASED ON "1-D Digital Waveguide Modeling for Improved Sound Synthesis".
文章/文档 This Document provides the High Level Design specification for the Bootloader development and librar
This Document provides the High Level Design specification for the Bootloader development and library porting for ADSP-BF533 based EZ-Kit Lite Board and STAMP Board. This document is meant to be the one of the inputs for the System Test Plan and the overall implementation of the same. This document ...
matlab例程 A general technique for the recovery of signicant image features is presented. The technique is ba
A general technique for the recovery of signicant
image features is presented. The technique is based on
the mean shift algorithm, a simple nonparametric pro-
cedure for estimating density gradients. Drawbacks of
the current methods (including robust clustering) are
avoided. Feature space of any nat ...
VHDL/FPGA/Verilog 基于FPGA的I2C总线模拟
基于FPGA的I2C总线模拟,采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.
行业发展研究 基于内容的新闻视频检索系统
基于内容的新闻视频检索系统,Study of Content-based News Video Retrieval System,优秀硕士论文
软件工程 书名:基本商业程序的建模 Essential Business Process Modeling (Paperback) 作者: Mike Havey 出版商:O Reilly 1 editio
书名:基本商业程序的建模
Essential Business Process Modeling (Paperback)
作者: Mike Havey
出版商:O Reilly 1 edition (August 18, 2005)
内容介绍:
Ten years ago, groupware bundled with email and calendar applications helped track the flow of work from person to person within an organization. Workflo ...
其他 In this paper we propose to reduce the textural components by modelling the coefficients of a wedg
In
this paper we propose to reduce the textural components by
modelling the coefficients of a wedgelet based regression tree
instead of the original pixel intensities