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找到约 2,118 项符合 RF Design 的查询结果

VHDL/FPGA/Verilog RF CMOS Low-Phase-Noise LC Oscillator Through Memory Reduction Tail Transistor

RF CMOS Low-Phase-Noise LC Oscillator Through Memory Reduction Tail Transistor
https://www.eeworm.com/dl/663/467968.html
下载: 27
查看: 1059

文章/文档 da control filter design in matlab simulink

da control filter design in matlab simulink
https://www.eeworm.com/dl/652/468642.html
下载: 91
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文章/文档 three_phase_four_wires_p_q design circuit in matlab&simulink

three_phase_four_wires_p_q design circuit in matlab&simulink
https://www.eeworm.com/dl/652/468651.html
下载: 118
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matlab例程 SIMC PID tunning(Multivriable feedback control analysisn and design)

SIMC PID tunning(Multivriable feedback control analysisn and design)
https://www.eeworm.com/dl/665/468894.html
下载: 181
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VC书籍 Windows程序设计 Operating Systems Design and Implementation,3E

Windows程序设计 Operating Systems Design and Implementation,3E
https://www.eeworm.com/dl/686/469290.html
下载: 29
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单片机开发 This software is developed to provide ease with controller design. For PID control, options are give

This software is developed to provide ease with controller design. For PID control, options are given to design and analyse the compensated and uncompensated system. You are free to choice among Proportional PI, PD and PID mode of control. Both frequency and time domain characteristics can be ob ...
https://www.eeworm.com/dl/648/469685.html
下载: 48
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系统设计方案 FIR filter design with unseperable window, seperable window, frequency sampling method

FIR filter design with unseperable window, seperable window, frequency sampling method
https://www.eeworm.com/dl/678/470140.html
下载: 174
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其他 本人RF电路设计课上的一个project。基于AWR公司MW Office仿真软件的一个FET混频器设计方案。

本人RF电路设计课上的一个project。基于AWR公司MW Office仿真软件的一个FET混频器设计方案。
https://www.eeworm.com/dl/534/470570.html
下载: 178
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VHDL/FPGA/Verilog Hardware Design with VHDL Design Example: UART

Hardware Design with VHDL Design Example: UART
https://www.eeworm.com/dl/663/470876.html
下载: 197
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VHDL/FPGA/Verilog VHDL Design of BCD to 7-segment decoder using PROM

VHDL Design of BCD to 7-segment decoder using PROM
https://www.eeworm.com/dl/663/470877.html
下载: 53
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