搜索：RESET - 虫虫下载站

驱动编程  16 relay output channels and 16 isolated digital input channels LED indicators to show activated

16 relay output channels and 16 isolated digital input channels LED indicators to show activated relays Jumper selectable Form A/Form B-type relay output channel Output status read-back Keep relay output values when hot system reset High-voltage isolation on input channels(2,500 VDC) Hi ESD pr ...

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其他  The first task at hand is to set up the endpoints appropriately for this example. The following code

The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6 as a Bulk IN endpoint, also 4x buffered of si ...

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单片机开发  SED1335驱动320x240图形液晶驱动演示程序接口情况表述： No: LCM ----- 52 --------------------- 1...VSS..... GND

SED1335驱动320x240图形液晶驱动演示程序接口情况表述： No: LCM ----- 52 --------------------- 1...VSS..... GND 地线 2...VDD..... +5V(VCC) 电源 3...VO ..... -Vadj Input 对比度负压调整输入 4...A0 ..... P2.0 寄存器选择信号,命令数据方式选择 5.../WR..... WR 写有效 6.../RD..... RD ...

https://www.eeworm.com/dl/648/271951.html

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单片机开发  液晶显示模块:CV9018A（98X64 点阵）模块驱动芯片:S6B0724(KS0724) MCU驱动口: SID------P1.7 SCLK-----P1.6 RS----

液晶显示模块:CV9018A（98X64 点阵）模块驱动芯片:S6B0724(KS0724) MCU驱动口: SID------P1.7 SCLK-----P1.6 RS-------P1.5 1=显示数据 0=控制指令 /RESET---P1.4 /CS1B----P1.3 R1=PAGE NO. R2=COLOUM NO. R3=DATA

https://www.eeworm.com/dl/648/271957.html

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单片机开发  rt12864m样例程序

rt12864m样例程序，管脚号管脚名称电平管脚功能描述 1 VSS 0V 电源地 2 VCC +5V 电源正 3 V0 - 对比度（亮度）调整 4 RS(CS） H/L RS="H",表示DB7--DB0为显示数据 4 RS(CS） H/L RS="L",表示DB7--DB0为显示指令数据 5 R/W(SID) H/L R/W="H",E="H",数据被读到DB7--DB0 5 R/W(SID) H/L R/W="L",E="H→L", DB7--DB0的数据 ...

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VHDL/FPGA/Verilog vhdl编写

vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output ...

https://www.eeworm.com/dl/663/292193.html

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VHDL/FPGA/Verilog 伪随机序列发生器的vhdl算法设计一个伪随机序列发生器

伪随机序列发生器的vhdl算法设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。

https://www.eeworm.com/dl/663/293863.html

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J2ME 计时器 Run mode: * - stop 0 - switch on backlight # - suspend/resume joystick - set next result

计时器 Run mode: * - stop 0 - switch on backlight # - suspend/resume joystick - set next result 1-9 - set result for member with this number Inspect mode: *,#,0 - reset and start UP,LEFT - show previous result 1-9 - show result for member with this number

https://www.eeworm.com/dl/660/313716.html

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VHDL/FPGA/Verilog VGA显示的例子（VHDL语言）

VGA显示的例子（VHDL语言），实现彩条显示，按键reset实现切换功能。

https://www.eeworm.com/dl/663/327327.html

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驱动编程  T3G的TD-SCDMA平台的驱动安装

T3G的TD-SCDMA平台的驱动安装，其中包括弹出弹出光驱，reset usb总线，然后安装驱动

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