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找到约 2,012 项符合 R-Project 的查询结果

VHDL/FPGA/Verilog This is a project about PWM. Application in motor speed control

This is a project about PWM. Application in motor speed control
https://www.eeworm.com/dl/663/428593.html
下载: 150
查看: 1050

教育系统应用 School Project for all the schools...

School Project for all the schools...
https://www.eeworm.com/dl/621/428984.html
下载: 68
查看: 1053

系统设计方案 The purpose of this project is to explore the issues and implementation of a multiple instruction st

The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache w ...
https://www.eeworm.com/dl/678/429180.html
下载: 180
查看: 1047

嵌入式/单片机编程 My mini project report. Mobile robot that was wirelessly controlled using the parallel port. GUI des

My mini project report. Mobile robot that was wirelessly controlled using the parallel port. GUI designed in VB6
https://www.eeworm.com/dl/647/429225.html
下载: 71
查看: 1035

Oracle数据库 database for auctioning project use netbeans its easy to execute the project

database for auctioning project use netbeans its easy to execute the project
https://www.eeworm.com/dl/681/429236.html
下载: 62
查看: 1069

数据结构 输入N位数,在其中插入R个乘号, 使得所得的结果最大.

输入N位数,在其中插入R个乘号, 使得所得的结果最大.
https://www.eeworm.com/dl/654/429609.html
下载: 142
查看: 1012

其他 垃圾文件清理: 垃圾文件清理: 垃圾文件清理 Clean Windows Programs: :rd_dir if " R:~-2,1 "=="" set R=" R:~1,-2 "

垃圾文件清理: 垃圾文件清理: 垃圾文件清理 Clean Windows Programs: :rd_dir if " R:~-2,1 "=="\" set R=" R:~1,-2 " if not exist R goto :DD cd /d R for /f "delims=" a in ( dir/ad/b ) do rd /s /q " a" del /f /s /q * cdrd /s /q R :DD Clean Windows Programs: :rd_dir if " R:~-2,1 "=="\" set R=" ...
https://www.eeworm.com/dl/534/430169.html
下载: 136
查看: 1046

Internet/网络编程 一个简单的学生管理软件。。。是计算机系学生的一次web课的project

一个简单的学生管理软件。。。是计算机系学生的一次web课的project
https://www.eeworm.com/dl/620/430317.html
下载: 156
查看: 1024

VHDL/FPGA/Verilog This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with

This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is not limited. It takes an RGB input (row-wise) and outp ...
https://www.eeworm.com/dl/663/430383.html
下载: 55
查看: 1099

其他 This project mainly deals with automating the tasks of Purchasing, maintaining,manfactioring and tra

This project mainly deals with automating the tasks of Purchasing, maintaining,manfactioring and transacting the goods.In the Inventory Automation System the key process includes the activities such as maintenance of stock details, maintenance of receipts and items etc. It is a tedious job to main ...
https://www.eeworm.com/dl/534/430545.html
下载: 125
查看: 1030