搜索结果
找到约 422 项符合
Pre-designed 的查询结果
并行计算 CLAWPACK is a software package designed to compute numerical solutions to hyperbolic partial differe
CLAWPACK is a software package designed to compute numerical solutions to hyperbolic partial differential equations using a wave propagation approach
其他 Lua is a powerful, light-weight programming language designed for extending applications. It is also
Lua is a powerful, light-weight programming language designed for extending applications. It is also frequently used as a general-purpose, stand-alone language. It combines simple procedural syntax (similar to Pascal) with powerful data description constructs based on associative arrays and extensib ...
行业发展研究 COM Component designed to make full screen scrolling maps easy, especially from Visual Basic. This i
COM Component designed to make full screen scrolling maps easy, especially from Visual Basic. This is the VC++ 6.0 source code of the graphics engine
DSP编程 The line echo canceller (LEC) is designed to provide the maximum attainable transparent voice qualit
The line echo canceller (LEC) is designed to provide the maximum attainable transparent voice quality for
de-echoing of a PSTN or POTS connection in voice-over-LAN systems with internal delays, or on a codec end of a telecom switch,基于TI 54X/55X平台
单片机开发 AVR 8个数码管显示时钟程序with make file document. it can run on ME300 MCU board which is designed by willar. C
AVR 8个数码管显示时钟程序with make file document. it can run on ME300 MCU board which is designed by willar. Copyright belongs to willar.
其他 PNG开放源接口 The interface has been designed to be as simple and intuitive as possible. It supports plo
PNG开放源接口 The interface has
been designed to be as simple and intuitive as possible. It supports plotting and reading in the RGB (red, green,
blue), HSV (hue, saturation, value/brightness) and CMYK (cyan, magenta, yellow, black) colour spaces, basic
shapes, scaling, bilinear interpolation, full ...
VHDL/FPGA/Verilog The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode
The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated
with Micron SDRAM models. The design is verified with timing constraints at
115 MHZ.
电子书籍 This document is designed to aid anyone considering whether to write an emulator for an arcade gam
This document is designed to aid anyone considering whether to write an
emulator for an arcade game machine. It will attempt to answer frequently
asked questions, give a step by step tutorial, and provide the resources
necessary for a capable programmer to begin work on an emulator for an
arcade ...
其他嵌入式/单片机内容 The Wifidog project is an open source captive portal solution. It was designed primarily for wireles
The Wifidog project is an open source captive portal solution. It was designed primarily for wireless community groups, but caters to various other business models as well. If you have questions about the wifidog project, they may be answered in the FAQ. You may also be interested in seeing some of ...
VHDL/FPGA/Verilog CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re
CF VHDL
The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.