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教程资料 Digital Down Converter Design based on FPGA

Digital Down Converter Design based on FPGA.
https://www.eeworm.com/dl/fpga/doc/17843.html
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教程资料 fpga based jpge 压缩算法

fpga based jpge 压缩算法,性能不错,
https://www.eeworm.com/dl/fpga/doc/17881.html
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教程资料 FPGA-based link layer chip S19202 configuration

FPGA-based link layer chip S19202 configuration
https://www.eeworm.com/dl/fpga/doc/18064.html
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教程资料 Run Pac-man Game Based on 8086/8088 FPGA IP Core

Run Pac-man Game Based on 8086/8088 FPGA IP Core
https://www.eeworm.com/dl/fpga/doc/18245.html
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教程资料 一篇关于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers

一篇关于CORDIC的文章A survey of CORDIC algorithms for FPGA based computers
https://www.eeworm.com/dl/fpga/doc/18505.html
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教程资料 something useful for communication,source code based on FPGA

something useful for communication,source code based on FPGA
https://www.eeworm.com/dl/fpga/doc/18543.html
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教程资料 On the design of an FPGA-Based OFDM modulator for IEEE 802.11a

On the design of an FPGA-Based OFDM modulator for IEEE 802.11a
https://www.eeworm.com/dl/fpga/doc/18603.html
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模拟电子 XS128之锁相环PLL

XS128之锁相环PLL
https://www.eeworm.com/dl/571/20556.html
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模拟电子 使用时钟PLL的源同步系统时序分析

使用时钟PLL的源同步系统时序分析一)回顾源同步时序计算Setup Margin = Min Clock Etch Delay – Max Data Etch Delay – Max Delay Skew – Setup TimeHold Margin = Min Data Etch Delay – Max Clock Etch Delay + Min Delay Skew + Data Rate – Hold Time下面解释以上公式中各参数的意义:Etch Delay:与常说的飞行时 ...
https://www.eeworm.com/dl/571/21401.html
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教程资料 Altera可重配置PLL使用手册0414-3

Altera可重配置PLL使用手册0414-3。
https://www.eeworm.com/dl/fpga/doc/32274.html
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