搜索：Output - 虫虫下载站

数值算法/人工智能  Batch version of the back-propagation algorithm. ％ Given a set of corresponding input-output pairs

Batch version of the back-propagation algorithm. ％ Given a set of corresponding input-output pairs and an initial network ％ [W1,W2,critvec,iter]=batbp(NetDef,W1,W2,PHI,Y,trparms) trains the ％ network with backpropagation. ％％ The activation functions must be either linear or tanh. The network ...

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人工智能/神经网络  Produces a matrix of derivatives of network output w.r.t. ％ each network weight for use in the func

Produces a matrix of derivatives of network output w.r.t. ％ each network weight for use in the functions NNPRUNE and NNFPE.

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VHDL/FPGA/Verilog verilog code 4-bit carry look-ahead adder output [3:0] s //summation output cout //carryout inpu

verilog code 4-bit carry look-ahead adder output [3:0] s //summation output cout //carryout input [3:0] i1 //input1 input [3:0] i2 //input2 input c0 //前一級進位

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VHDL/FPGA/Verilog verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input

verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0

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VHDL/FPGA/Verilog verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y

verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y

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VHDL/FPGA/Verilog verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient

verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient output [8:0]Remainder

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其他  编写input()和output()函数输入

编写input()和output()函数输入，输出5个学生的数据记录，主要练习使用这两个函数

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单片机开发  本例展示了如何设置TIM工作在输出比较-非主动模式（Output Compare Inactive mode）

本例展示了如何设置TIM工作在输出比较-非主动模式（Output Compare Inactive mode），并产生相应的中断。 TIM2时钟设置为36MHz，预分频设置为35999，TIM2计数器时钟可表达为： TIM2 counter clock = TIMxCLK / (Prescaler +1) = 1 KHz 设置TIM2_CCR1寄存器值为1000， CCR1寄存器值1000除以TIM2计数器时钟频率1KHz，为1000 ...

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单片机开发  OC0 output mode 设定了pwm输出控制选择

OC0 output mode 设定了pwm输出控制选择

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其他  Input : A set S of planar points Output : A convex hull for S Step 1: If S contains no more than f

Input : A set S of planar points Output : A convex hull for S Step 1: If S contains no more than five points, use exhaustive searching to find the convex hull and return. Step 2: Find a median line perpendicular to the X-axis which divides S into SL and SR SL lies to the left of SR . Step 3: Recursi ...

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