搜索结果
找到约 3,129 项符合
NC-Verilog 的查询结果
可编程逻辑 XAPP143-利用Verilog来创建CPLD设计
This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state m ...
可编程逻辑 Verilog编码中的非阻塞性赋值
 
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...
可编程逻辑 Verilog Coding Style for Efficient Digital Design
 
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All the ...
可编程逻辑 VHDL,Verilog,System verilog比较
 
本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers ...
可编程逻辑 基于Verilog HDL设计的多功能数字钟
本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟，突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点，并通过Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成综合、仿真。此程序通过下载到FPGA 芯片后，可应用于实际的数字钟显示中。
关键词：Verilog HDL；硬件描述语言；FPGA
Abstract: In this ...
加密解密 DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。
DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。
VHDL/FPGA/Verilog 本文为verilog的源代码
本文为verilog的源代码
文章/文档 Verilog编码与综合中的非阻塞性赋值
Verilog编码与综合中的非阻塞性赋值
嵌入式/单片机编程 8位RISC CPU的VERILOG编程 SOURCECODE
8位RISC CPU的VERILOG编程 SOURCECODE
嵌入式/单片机编程 Verilog DHL教程
Verilog DHL教程