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其他书籍 本软件提供了VC++中调用Matlab.m函数编译后的动态链接库.Matlab的数值处理能力很强,用VC++调用Matlab函数可以解决很多问题
本软件提供了VC++中调用Matlab.m函数编译后的动态链接库.Matlab的数值处理能力很强,用VC++调用Matlab函数可以解决很多问题
数据结构 一种基于二维链表的稀疏矩阵模半板类设计 A template Class of sparse matrix. Key technology: bin,2-m linked matrix. con
一种基于二维链表的稀疏矩阵模半板类设计
A template Class of sparse matrix.
Key technology: bin,2-m linked matrix.
constructors: 1.normal constuctor 2.copy constuctor. 3.assignment constructor.
Basic operator: 1. addition(sub) of two matrix
2. inverse of a matrix.
3. multiply of two matrix.
etc ...
Linux/Unix编程 The Reed-Somolon code is specified by the finite field, the length (length <= 2^m-1), the numbe
The Reed-Somolon code is specified by the finite field, the length
(length <= 2^m-1), the number of redundant symbols (length-k), and
the initial zero of the code, init_zero, such that the zeros are:
init_zero, init_zero+1, ..., init_zero+length-k-1
Windows CE Freescale IMX31 ADS CS8900a Head file, it is very important
Freescale IMX31 ADS CS8900a Head file, it is very important
Windows CE Freescale IMX31 ADS board iic driver interrupt file,very important
Freescale IMX31 ADS board iic driver interrupt file,very important
Windows CE Freescale IMX31 ADS Demo board backlight driver file , please be secret
Freescale IMX31 ADS Demo board backlight driver file , please be secret
文件格式 标准mpeg4 File Formate ,通过学习可了解mpeg4文件得格式. 对做mpeg2 Player有帮助.
标准mpeg4 File Formate ,通过学习可了解mpeg4文件得格式.
对做mpeg2 Player有帮助.
VHDL/FPGA/Verilog /* This program generates the DApkg.vhd file that is used to define * the DA filter core and give
/* This program generates the DApkg.vhd file that is used to define
* the DA filter core and gives its parameters and the contents of the
* Distributed Arithmetic Look-up-table "DALUT" according to the DA algorithm
VHDL/FPGA/Verilog IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at
IDCT-M is a medium speed 1D IDCT core
-- it can accept a continous stream of 12-bit input words at a rate of
-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video
-- the core is 100％ synthesizable
VHDL/FPGA/Verilog -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can r
-- Title : Barrel Shifter (Pure combinational)
-- This VHDL design file is an open design you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at