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开发工具 pads2007logic中文教程下载

PADS 2007 LOGIC中文教程 希望对大家有所帮助~~~
https://www.eeworm.com/dl/550/37607.html
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开发工具 EDA增强工具

本软件是多种EDA软件的鼠标增强工具,绿色单文件,支持Win9x/NT/2000/XP/WIN7,其中WIN7需要以管理员模式运行,另外,Win9x需要编译成非UNICODE版本,有需要的用户可发邮件给我索取,支持protel99se,DXP(AD),PADS,OrCAD的capture、Cam350、Saber、PC Schematic、Allegro、CircuitCAM,并且对每个软件的功能都可设置,用户 ...
https://www.eeworm.com/dl/550/37950.html
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实用工具 MAXQUSBJTAGOW评估板软件

MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1 ...
https://www.eeworm.com/dl/551/38236.html
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实用工具 pads2007logic中文教程下载

PADS 2007 LOGIC中文教程 希望对大家有所帮助~~~
https://www.eeworm.com/dl/551/38251.html
下载: 167
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实用工具 EDA增强工具

本软件是多种EDA软件的鼠标增强工具,绿色单文件,支持Win9x/NT/2000/XP/WIN7,其中WIN7需要以管理员模式运行,另外,Win9x需要编译成非UNICODE版本,有需要的用户可发邮件给我索取,支持protel99se,DXP(AD),PADS,OrCAD的capture、Cam350、Saber、PC Schematic、Allegro、CircuitCAM,并且对每个软件的功能都可设置,用户 ...
https://www.eeworm.com/dl/551/38548.html
下载: 129
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可编程逻辑 Allegro FPGA System Planner中文介绍

  完整性高的FPGA-PCB系统化协同设计工具   Cadence OrCAD and Allegro FPGA System Planner便可满足较复杂的设计及在设计初级产生最佳的I/O引脚规划,并可透过FSP做系统化的设计规划,同时整合logic、schematic、PCB同步规划单个或多个FPGA pin的最佳化及layout placement,借由整合式的界面以减少重复在design及P ...
https://www.eeworm.com/dl/kbcluoji/38902.html
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可编程逻辑 Create a 1-Wire Master with Xilinx PicoBlaze

Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wir ...
https://www.eeworm.com/dl/kbcluoji/39318.html
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可编程逻辑 Nios II定制指令用户指南

     Nios II定制指令用户指南:With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequen ...
https://www.eeworm.com/dl/kbcluoji/39394.html
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可编程逻辑 Verilog_HDL的基本语法详解(夏宇闻版)

        Verilog_HDL的基本语法详解(夏宇闻版):Verilog HDL是一种用于数字逻辑电路设计的语言。用Verilog HDL描述的电路设计就是该电路的Verilog HDL模型。Verilog HDL既是一种行为描述的语言也是一种结构描述的语言。这也就是说,既可以用电路的功能描述也可以用元器件和它们之 ...
https://www.eeworm.com/dl/kbcluoji/39407.html
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可编程逻辑 Analog Solutions for Altera FPGAs

Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells calle ...
https://www.eeworm.com/dl/kbcluoji/39953.html
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