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matlab例程 amer s noise level estimation implementation on MATLAB

amer s noise level estimation implementation on MATLAB
https://www.eeworm.com/dl/665/404971.html
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驱动编程 The SP486 and SP487 are low–power quad differential line drivers meeting RS-485 and RS-422 standard

The SP486 and SP487 are low–power quad differential line drivers meeting RS-485 and RS-422 standards. The SP486 features a common driver enable control the SP487 provides independent driver enable controls for each pair of drivers. Both feature tri–state outputs and wide common–mode input range. ...
https://www.eeworm.com/dl/618/406947.html
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语音压缩 Melp Federal Vocoder 2.4 kbps low bit rate high qualitytexas instrument Melp encoder decoder c-code

Melp Federal Vocoder 2.4 kbps low bit rate high qualitytexas instrument Melp encoder decoder c-code working great with good quality melp vocoding system
https://www.eeworm.com/dl/627/408109.html
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matlab例程 This file is hysterisis two level controller

This file is hysterisis two level controller
https://www.eeworm.com/dl/665/412302.html
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Windows Mobile Example of using HTC sensor api to get Light sensor value and set backlight level in modern HTC phon

Example of using HTC sensor api to get Light sensor value and set backlight level in modern HTC phones. This app will replace original autobacklight level regulator and add more customizable options.
https://www.eeworm.com/dl/677/412759.html
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3G开发 This is the Low Energy Adaptive Clustering Hierarchy routing protocol [LEACH] source code for wirele

This is the Low Energy Adaptive Clustering Hierarchy routing protocol [LEACH] source code for wireless sensor network we have used.It is developed with MatLab7
https://www.eeworm.com/dl/701/416192.html
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VHDL/FPGA/Verilog Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the sub-circuits can be used as smaller benchmarks.
https://www.eeworm.com/dl/663/416926.html
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VHDL/FPGA/Verilog Very low cost, low component count charger/adapter – replaces linear transformer based solutions &#

Very low cost, low component count charger/adapter – replaces linear transformer based solutions &#8226 Extremely simple circuit configuration designed for high volume, low cost manufacturing
https://www.eeworm.com/dl/663/419953.html
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matlab例程 Very low cost, low component count charger/adapter – replaces linear transformer based solutions &#

Very low cost, low component count charger/adapter – replaces linear transformer based solutions &#8226 Extremely simple circuit configuration designed for high volume, low cost manufacturing
https://www.eeworm.com/dl/665/419956.html
下载: 145
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系统设计方案 Top Level Dual Port Ram Core Project, VHDL code

Top Level Dual Port Ram Core Project, VHDL code
https://www.eeworm.com/dl/678/423926.html
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