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https://www.eeworm.com/dl/617/255254.html 压缩解压

the implementation of an Embedded Zerotree Wavelet encoder or EZW encoder

the implementation of an Embedded Zerotree Wavelet encoder or EZW encoder
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https://www.eeworm.com/dl/542/194974.html 其他书籍

MAODV教学in NS-2.2.6 MAODV Implementation for NS-2.26

MAODV教学in NS-2.2.6 MAODV Implementation for NS-2.26
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https://www.eeworm.com/dl/652/169570.html 文章/文档

RTK Networks based on Geo++&reg GNSMART &#8722 Concepts, Implementation, Results

RTK Networks based on Geo++&reg GNSMART &#8722 Concepts, Implementation, Results
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https://www.eeworm.com/dl/542/204606.html 其他书籍

Realtime Operating Systems Concepts and Implementation of Microkernels for Embedded Systems

Realtime Operating Systems Concepts and Implementation of Microkernels for Embedded Systems
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https://www.eeworm.com/dl/617/206149.html 压缩解压

MATLAB implementation of SPIHT (without Arithmatic coding stage). ％ Performance evaluation : this

MATLAB implementation of SPIHT (without Arithmatic coding stage). ％ Performance evaluation : this toolbox VS. SPIHT ％ Test image: lena512.raw ％ bpp SPIHT(dB) This code(dB) ％ 0.1000 29.8107 29.3202 ％ 0.2000 32.7202 32.2514 ％ 0.3000 34.5479 34.0331 ％ 0.4000 35.8422 35.4857 ...
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https://www.eeworm.com/dl/663/184645.html VHDL/FPGA/Verilog

usb_cpld_code.zip usbjtag - Variations on the implementation of a USB JTAG adapter.

usb_cpld_code.zip usbjtag - Variations on the implementation of a USB JTAG adapter.
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https://www.eeworm.com/dl/646/437515.html 通讯编程文档

Description of a sistolic arhictecture for a FFT implementation in FPGA.

Description of a sistolic arhictecture for a FFT implementation in FPGA.
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https://www.eeworm.com/dl/646/437526.html 通讯编程文档

Description of a high performance FFT architecture useful for VLSI implementation.

Description of a high performance FFT architecture useful for VLSI implementation.
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https://www.eeworm.com/dl/692/438721.html 行业发展研究

Multi interface implementation document for NS-2 for ad hoc network

Multi interface implementation document for NS-2 for ad hoc network
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https://www.eeworm.com/dl/663/413255.html VHDL/FPGA/Verilog

Hardware UDP, implementation of UDP based on Altera DE2 using Verilog

Hardware UDP, implementation of UDP based on Altera DE2 using Verilog
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