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https://www.eeworm.com/dl/635/196768.html 网络

基于chord算法的p2p文件系统。A p2p file system based on chord.

基于chord算法的p2p文件系统。A p2p file system based on chord.
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https://www.eeworm.com/dl/644/197606.html 汇编语言

PC Assembly Tutorial running the code in the tutorial, you need get the appropriate zip file of thi

PC Assembly Tutorial running the code in the tutorial, you need get the appropriate zip file of this!
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https://www.eeworm.com/dl/650/198173.html 人工智能/神经网络

this m file can Find a (near) optimal solution to the Traveling Salesman Problem (TSP) by setting up

this m file can Find a (near) optimal solution to the Traveling Salesman Problem (TSP) by setting up a Genetic Algorithm (GA) to search for the shortest path (least distance needed to travel to each city exactly once) Notes: 1. Input error checking included 2. Inputs can be speci ...
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https://www.eeworm.com/dl/534/201814.html 其他

This m file analyzes a coherent binary phase shift keyed(BPSK) and a amplitude shift keyed(ASK) comm

This m file analyzes a coherent binary phase shift keyed(BPSK) and a amplitude shift keyed(ASK) communication system. The receiver uses a correlator(mixer-integrator[LPF]) configuration with BER measurements comparing measured and theoretical results. The bandpass and low pass us ...
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https://www.eeworm.com/dl/640/359668.html CA认证

creat a certificate using makecert creat a PKCS#12.pfx file to store the private key Encrypte data

creat a certificate using makecert creat a PKCS#12.pfx file to store the private key Encrypte data using the public Key in Certificate Decrypt data using the private key in a PKCS#12.pfx file
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https://www.eeworm.com/dl/527/360684.html 通讯/手机编程

iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control

iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2 ...
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https://www.eeworm.com/dl/663/361747.html VHDL/FPGA/Verilog

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shi ...
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https://www.eeworm.com/dl/663/361749.html VHDL/FPGA/Verilog

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shi ...
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https://www.eeworm.com/dl/527/299357.html 通讯/手机编程

M-file uses random data which BPSK modulates a carrier to configure a BPSK UWB transmitter. The rece

M-file uses random data which BPSK modulates a carrier to configure a BPSK UWB transmitter. The receiver demodulates the BPSK UWB carrier and the data is recovered.
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https://www.eeworm.com/dl/687/301692.html 其他嵌入式/单片机内容

The schematic is at foler schematic. The hex file is at foler default. You can compiler the code

The schematic is at foler schematic. The hex file is at foler default. You can compiler the code yourself using AvrStudio4.13 b528 + WinAVR200701
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