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可编程逻辑 Nios II软件构建工具入门
Nios II软件构建工具入门
The Nios® II Software Build Tools (SBT) allows you to construct a wide variety of
complex embedded software systems using a command-line interface. From this
interface, you can execute Software Built Tools command utilities, and use scripts
other tools) to combine the com ...
可编程逻辑 使用Nios II软件构建工具
 使用Nios II软件构建工具
This chapter describes the Nios® II Software Build Tools (SBT), a set of utilities and
scripts that creates and builds embedded C/C++ application projects, user library
projects, and board support packages (BSPs). The Nios II SBT supports a repeatable,
scriptable, a ...
可编程逻辑 使用Nios II紧耦合存储器教程
             使用Nios II紧耦合存储器教程
Chapter 1. Using Tightly Coupled Memory with the Nios II Processor
Reasons for Using Tightly Coupled Memory  . . . . . . . . . . . . . . . . . . . . . . . 1–1
Tradeoffs  . . . . . . . ...
可编程逻辑 Nios II定制指令用户指南
     Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom
instructions, you can reduce a complex sequen ...
可编程逻辑 AN522: Implementing Bus LVDS
This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
可编程逻辑 XAPP424 - 嵌入式JTAG ACE播放器
This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing desi ...
可编程逻辑 xapp069 - 使用XC9500 JTAG边界扫描接口
This application note explains the XC9500™/XL/XV Boundary Scan interface anddemonstrates the software available for programming and testing XC9500/XL/XV CPLDs. Anappendix summarizes the iMPACT software operations and provides an overview of theadditional operations supported by XC9500/XL/XV ...
可编程逻辑 XAPP144 -设计CPLD多电压系统
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for han ...
可编程逻辑 PLB Block RAM(BRAM)接口控制器
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
可编程逻辑 XAPP953-二维列序滤波器的实现
 
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horiz ...