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汇编语言 Interfacing H1632 with PIC 18F452

Interfacing H1632 with PIC 18F452
https://www.eeworm.com/dl/644/494132.html
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DSP编程 Interfacing the MSP430 With a DSP Application

Interfacing the MSP430 With a DSP Application
https://www.eeworm.com/dl/516/494315.html
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电源技术 雪崩光电二极管的偏置电压和电流检测电路

  Avalanche photodiodes (APDs) are widely utilized in laserbased fiberoptic systems to convert optical data intoelectrical form. The APD is usually packaged with a signalconditioning amplifier in a small module. An APD receivermodule and attendant circuitry appears in Figure 1. TheAPD modul ...
https://www.eeworm.com/dl/505/24376.html
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单片机编程 PROTEUS VSM在单片机系统仿真中的应用

PROTEUS VSM在单片机系统仿真中的应用::介绍了单片机系统仿真工具PROTEUS VSM 及其在单片机系统仿真中的应用,给出了具体的应用实例,详细地介绍了PROTEUS VSM 与Keil uVision3的接口方法。关键词:单片机;Keil uVision3;仿真;外围器件;PROTEUS VSM; Abstract:This paper introduces the simulation tool for M CU s ...
https://www.eeworm.com/dl/502/30555.html
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单片机编程 Using the P82B96 for bus inter

The P82B96 offers many different ways in which it can be used as abus interface. In its simplest application it can be used as aninterface between bus systems operating from different supplyvoltages. Opto isolation between two bus systems is possible, andalso the availability of the Tx and Rx signal ...
https://www.eeworm.com/dl/502/31091.html
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教程资料 XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接  The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and ...
https://www.eeworm.com/dl/fpga/doc/32622.html
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可编程逻辑 XAPP144 -设计CPLD多电压系统

Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for han ...
https://www.eeworm.com/dl/kbcluoji/40067.html
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可编程逻辑 XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接  The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and ...
https://www.eeworm.com/dl/kbcluoji/40104.html
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接口技术 基于微处理器的5V系统接口

This application note discusses a variety of approaches for interfacing analog signals to 5V powered systems. Synthesizing a "rail-to-rail" op amp and scaling techniques for A/D converters are covered. A voltage-to-frequency converter, applicable where high resolution is required, is also presente ...
https://www.eeworm.com/dl/511/42418.html
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其他 As science advances, novel experiments are becoming more and more complex, requiring a zoo of contro

As science advances, novel experiments are becoming more and more complex, requiring a zoo of control devices and electronics executing complicated sequences of steps. Device availability and monetary constrains usually lead to a highly heterogeneous setup with components from several different manu ...
https://www.eeworm.com/dl/534/280620.html
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