搜索结果

找到约 861 项符合 High-efficiency 的查询结果

其他 an approach for capturing similarity between words that was concerned with the syntactic similarity

an approach for capturing similarity between words that was concerned with the syntactic similarity of two strings. Today we are back to discuss another approach that is more concerned with the meaning of words. Semantic similarity is a confidence score that reflects the semantic relation between th ...
https://www.eeworm.com/dl/534/346309.html
下载: 87
查看: 1071

文章/文档 In the previous article, we presented an approach for capturing similarity between words that was co

In the previous article, we presented an approach for capturing similarity between words that was concerned with the syntactic similarity of two strings. Today we are back to discuss another approach that is more concerned with the meaning of words. Semantic similarity is a confidence score that ref ...
https://www.eeworm.com/dl/652/346312.html
下载: 52
查看: 1050

Internet/网络编程 IEEE 802.11a-1999 (8802-11:1999/Amd 1:2000(E)), IEEE Standard for Information technology—Telecommuni

IEEE 802.11a-1999 (8802-11:1999/Amd 1:2000(E)), IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements—Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specification ...
https://www.eeworm.com/dl/620/349001.html
下载: 109
查看: 1041

Java书籍 Writing Robust Java Code The AmbySoft Inc. Coding Standards for Java v17.01d Scott W. Ambler Sof

Writing Robust Java Code The AmbySoft Inc. Coding Standards for Java v17.01d Scott W. Ambler Software Process Mentor This Version: January 15, 2000 Copyright 1998-1999 AmbySoft Inc.Purpose of this White Paper This white paper describes a collection of standards, conventio code. They are based on so ...
https://www.eeworm.com/dl/656/349056.html
下载: 101
查看: 1041

通讯/手机编程 sim 文件系统In addition, its quality of service reduces because of reliance on traditional circuit-switc

sim 文件系统In addition, its quality of service reduces because of reliance on traditional circuit-switched network elements. At that former time, people hoped to build a based system, which could access a centralized server network, would always have access to the latest traffic information and cou ...
https://www.eeworm.com/dl/527/351888.html
下载: 164
查看: 1034

其他书籍 Because of the poor observability of Inertial Navigation System on stationary base, the estimation

Because of the poor observability of Inertial Navigation System on stationary base, the estimation error of the azimuth will converge very slowly in initial alignment by means of Kalmari filtering, and making the time initial alignment is longer. In this paper, a fast estimation method of the azimut ...
https://www.eeworm.com/dl/542/355776.html
下载: 176
查看: 1052

通讯编程文档 With the advent of multimedia, digital signal processing (DSP) of sound has emerged from the shadow

With the advent of multimedia, digital signal processing (DSP) of sound has emerged from the shadow of bandwidth-limited speech processing. Today, the main appli- cations of audio DSP are high quality audio coding and the digital generation and manipulation of music signals. They share common resear ...
https://www.eeworm.com/dl/646/358921.html
下载: 121
查看: 1044

其他书籍 A few short years ago, the applications for video were somewhat confined—analog was used for broad

A few short years ago, the applications for video were somewhat confined—analog was used for broadcast and cable television, VCRs, set-top boxes, televisions and camcorders. Since then, there has been a tremendous and rapid conversion to digital video, mostly based on the MPEG-2 video compression s ...
https://www.eeworm.com/dl/542/360043.html
下载: 136
查看: 1091

VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift ...
https://www.eeworm.com/dl/663/361747.html
下载: 164
查看: 1055

VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift ...
https://www.eeworm.com/dl/663/361749.html
下载: 129
查看: 1034