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C/C++语言编程 基于(英蓓特)STM32V100的看门狗程序

This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent ...
https://www.eeworm.com/dl/503/37359.html
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开发工具 Foundation入门—仿真

Explain how to open the Waveform Viewer for Verification ? State how to insert nodes into the Waveform Viewer ? Tell how to assign Stimulus with the Stimulator Selector
https://www.eeworm.com/dl/550/38037.html
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可编程逻辑 MAX20021,MAX20022示例PCB布局指南

Abstract: This application note explains how to layout the MAX20021/MAX20022 automotive quad powermanagementICs (PMICs) to maximize performance and minimize emissions. Example images of a fourlayerlayout are provided.
https://www.eeworm.com/dl/kbcluoji/38886.html
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可编程逻辑 Xilinx的Zynq可扩展式处理平台(EPP)电子教材

Abstract: This reference design explains how to power the Xilinx Zynq Extensible Processing Platform (EPP) and peripheral ICs using
https://www.eeworm.com/dl/kbcluoji/39621.html
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可编程逻辑 AN522: Implementing Bus LVDS

This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
https://www.eeworm.com/dl/kbcluoji/39867.html
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可编程逻辑 XAPP694-从配置PROM读取用户数据

This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in t ...
https://www.eeworm.com/dl/kbcluoji/40049.html
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可编程逻辑 XAPP122 - Spartan-XL FPGA的Express配置

Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express con ...
https://www.eeworm.com/dl/kbcluoji/40057.html
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可编程逻辑 XAPP098 - Spartan FPGA低成本、高效率串行配置

This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration ci ...
https://www.eeworm.com/dl/kbcluoji/40059.html
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可编程逻辑 XAPP143-利用Verilog来创建CPLD设计

This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state m ...
https://www.eeworm.com/dl/kbcluoji/40069.html
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可编程逻辑 WP401-FPGA设计的DO-254

The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard ...
https://www.eeworm.com/dl/kbcluoji/40071.html
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