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matlab例程 JLAB is a set of Matlab functions I have written or co-written over the past fifteen years for the p
JLAB is a set of Matlab functions I have written or co-written over the past fifteen years for the purpose of analyzing data. It consists of four hundred m-files spanning thirty thousand lines of code. JLAB includes functions ranging in complexity from one-line aliases to high-level algorithms for c ...
数学计算 LAPACK++ (Linear Algebra PACKage in C++) is a software library for numerical linear algebra that sol
LAPACK++ (Linear Algebra PACKage in C++) is a software library for numerical linear algebra that solves systems of linear equations and eigenvalue problems on high performance computer architectures
VHDL/FPGA/Verilog Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet high
Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C
软件工程 This version of the book is a DRAFT! The chapters are mostly complete, but not carefully edited. Som
This version of the book is a DRAFT! The chapters are mostly complete, but not carefully edited. Some of the debugging sections are not done, and not all chapters have exercises.
If you have high-level comments about the organization of the book or the topics covered, please send me email at feedb ...
SCSI/ASPI 一个iscsi实现源码
一个iscsi实现源码，值得参考。It is a high-performance, transport independent,
multi-platform implementation of RFC3720 iSCSI.
单片机开发 A major goal of this book is to show to make devices that are inherently reliable by design. While a
A major goal of this book is to show to make devices that are inherently reliable by design. While a lot of attention has been given to “quality improvement,” the majority of the emphasis has been placed on the processes that occur after the design of a product is complete. Design deficiencies are ...
其他 Microsoft Visual C++
Microsoft Visual C++，Borland C++，Watcom C++ ,Borland C++ ，Borland C++ Builder,Borland C++ 3.1 for DOS,Watcom C++ 11.0 for DOS,GNU DJGPP C++ ，Lccwin32 C Compiler 3.1,Microsoft C,High C
VHDL/FPGA/Verilog -- DESCRIPTION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right
-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
-- Shift direction: right/left (right active high)
--
-- CLK active : high
-- CLR active : high
-- CLR type : synchronous
-- SET active : high
-- SET type : synchronous
-- LOAD active : high
-- CE active : high
-- SERIAL input : SI ...
单片机开发 DESCRIPTION : BIN to seven segments converter -- segment encoding -- a -- +---+ -- f | | b --
DESCRIPTION : BIN to seven segments converter
-- segment encoding
-- a
-- +---+
-- f | | b
-- +---+ <- g
-- e | | c
-- +---+
-- d
-- Enable (EN) active : high
-- Outputs (data_out) active : low
文章/文档 ITU的关于图像主观质量评价的标准文档
ITU的关于图像主观质量评价的标准文档，具体描述了double-stimulus continuous quality-scale (DSCQS)的测试条件和方法