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嵌入式综合 1-Wire总线主机
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implem ...
嵌入式综合 针对Xilinx FPGA的电源解决方案
Abstract: Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signalprocessing, medical imaging, and high-performance computing. This application note outlines the issues related to powering FPGAs.It also discusses Maxim's soluti ...
嵌入式综合 WP276 -可编程的开发和测试
We all know the benefits of using FieldProgrammable Gate Arrays (FPGAs): no NRE, nominimum order quantities, and faster time-tomarket.In an ideal world, designs would never needto be changed because of design errors, but we allknow that sometimes this is necessary.
可编程逻辑 Create a 1-Wire Master with Xilinx PicoBlaze
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wir ...
可编程逻辑 Verilog_HDL的基本语法详解（夏宇闻版）
        Verilog_HDL的基本语法详解（夏宇闻版）:Verilog HDL是一种用于数字逻辑电路设计的语言。用Verilog HDL描述的电路设计就是该电路的Verilog HDL模型。Verilog HDL既是一种行为描述的语言也是一种结构描述的语言。这也就是说，既可以用电路的功能描述也可以用元器件和它们之 ...
可编程逻辑 WP200-将Spartan-3 FPGA用作远程数码相机的低成本控制器
 
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for ...
可编程逻辑 WP312-Xilinx新一代28nm FPGA技术简介
Xilinx Next Generation 28 nm FPGA Technology Overview
Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. ...
可编程逻辑 Verilog Coding Style for Efficient Digital Design
 
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All the ...
可编程逻辑 CPLD和FPGA设计介绍
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system ...
软件工程 In most software-development organizations, the testing program functions as the final "quality gat
In most software-development organizations, the testing program functions as the
final "quality gate" for an application, allowing or preventing the move from the
comfort of the software-engineering environment into the real world. With this role
comes a large responsibility: The success of an appli ...