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编译器/解释器 This is the source for a C compiler that generates 386 or m68K code. Code generation is fairly good
This is the source for a C compiler that generates 386 or
m68K code. Code generation is fairly good although the optimizer is
a little naive... the code itself should be highly portable although
there are some issues involved with porting from MSDOS that have to
be resolved for example the size of L ...
Java编程 This the first release (version 0.0) of the Peersim high level P2P network simulator. This archi
This the first release (version 0.0) of the Peersim
high level P2P network simulator.
This archive contains the javadoc generated documentation,
and a java archive containing the simulator source and bytecode
and some examples.
单片机开发 实现8比特字节的RS纠错编码
实现8比特字节的RS纠错编码，可以指定极性校验字节数目，能产生的最大校验序列长度为255字节（含极性校验字节）.This is an implementation of a Reed-Solomon code with 8 bit bytes, and a configurable number of parity bytes. The maximum sequence length (codeword) that can be generated is 255 bytes, including ...
编译器/解释器 This the source for a C compiler that generates 386 or m68K code. Code generation is fairly good al
This the source for a C compiler that generates 386 or
m68K code. Code generation is fairly good although the optimizer is
a little naive... the code itself should be highly portable although
there are some issues involved with porting from MSDOS that have to
be resolved for example the size of LONG ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
数学计算 The inverse of the gradient function. I ve provided versions that work on 1-d vectors, or 2-d or 3-d
The inverse of the gradient function. I ve provided versions that work on 1-d vectors, or 2-d or 3-d arrays. In the 1-d case I offer 5 different methods, from cumtrapz, and an integrated cubic spline, plus several finite difference methods.
In higher dimensions, only a finite difference/linear alge ...
微处理器开发 ST32 基于（英蓓特）STM32V100的EXTI程序 This example shows how to configure an external interrupt line. In t
ST32
基于（英蓓特）STM32V100的EXTI程序
This example shows how to configure an external interrupt line.
In this example, the EXTI line 9 is configured to generate an interrupt on each
falling edge. In the interrupt routine a led connected to PC.06 is toggled.
This led will be toggled due to the softa ...
其他 We propose a technique that allows a person to design a new photograph with substantially less effo
We propose a technique that allows a person to design a new photograph
with substantially less effort. This paper presents a method that generates a composite image when a user types
in nouns, such as “boat” and “sand.” The artist can optionally design an intended image by specifying other
const ...
单片机开发 The DHRY program performs the dhrystone benchmarks on the 8051. Dhrystone is a general-performanc
The DHRY program performs the dhrystone benchmarks on the 8051.
Dhrystone is a general-performance benchmark test originally
developed by Reinhold Weicker in 1984. This benchmark is
used to measure and compare the performance of different
computers or, in this case, the efficiency of the code
gener ...