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VC书籍 This book is for you if You re no "dummy," and you need to get quickly up to speed in intermediate

This book is for you if You re no "dummy," and you need to get quickly up to speed in intermediate to advanced C++ You ve had some experience in C++ programming, but reading intermediate and advanced C++ books is slow-going You ve had an introductory C++ course, but you ve found that you still can t ...
https://www.eeworm.com/dl/686/350755.html
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Java书籍 SSD3: Object-Oriented Programming and Design Introduction This course introduces students to prob

SSD3: Object-Oriented Programming and Design Introduction This course introduces students to problem solving by means of object-oriented design and implementation. Emphasis is on problem analysis and solution design, documentation and implementation. Students use commercial software libraries, and ...
https://www.eeworm.com/dl/656/351830.html
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USB编程 使用68013的测试程序

使用68013的测试程序,包含68013固件程序(采用slave FIFO bulk同步读写,EP2 OUT,EP6 IN),驱动,PC端测试用程序。CPLD的VHDL代码
https://www.eeworm.com/dl/643/355352.html
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其他书籍 Recent advances in experimental methods have resulted in the generation of enormous volumes of data

Recent advances in experimental methods have resulted in the generation of enormous volumes of data across the life sciences. Hence clustering and classification techniques that were once predominantly the domain of ecologists are now being used more widely. This book provides an overview of these i ...
https://www.eeworm.com/dl/542/357867.html
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数值算法/人工智能 谭浩强C课件

谭浩强C课件,tanhaoqiang C,first part
https://www.eeworm.com/dl/518/361178.html
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VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift ...
https://www.eeworm.com/dl/663/361747.html
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VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift ...
https://www.eeworm.com/dl/663/361749.html
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语音压缩 The files in this directory comprise ANSI-C language reference implementations of the CCITT (Intern

The files in this directory comprise ANSI-C language reference implementations of the CCITT (International Telegraph and Telephone Consultative Committee) G.711, G.721 and G.723 voice compressions. They have been tested on Sun SPARCstations and passed 82 out of 84 test vectors published by CCITT (De ...
https://www.eeworm.com/dl/627/362279.html
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Java编程 Produce Java classes to calculate and display the Poisson probability when input the value of the av

Produce Java classes to calculate and display the Poisson probability when input the value of the average (A) arrival rate of customers at some business in the range of 1 to 10. The error message will output when A is out of the range。
https://www.eeworm.com/dl/633/362711.html
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软件设计/软件工程 进入CCS环境

进入CCS环境,装载已有工程,并load生成的.out文件,并找到要察看代码执行周期的代码处。
https://www.eeworm.com/dl/684/365261.html
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