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VHDL/FPGA/Verilog The Free IP Project VHDL Free-RAM Core

The Free IP Project VHDL Free-RAM Core
https://www.eeworm.com/dl/663/381032.html
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其他书籍 This program is free software you can redistribute it and/or modify // it under the terms of the GN

This program is free software you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation either version 2 of the License, or // (at your option) any later version.
https://www.eeworm.com/dl/542/381304.html
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压缩解压 The ZZIPlib provides read access on ZIP-archives. The library uses only the patent-free compression-

The ZZIPlib provides read access on ZIP-archives. The library uses only the patent-free compression-algorithms supported by Zlib. It provides functions that transparently access files being either real files or zipped files, both with the same filepath
https://www.eeworm.com/dl/617/386667.html
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软件设计/软件工程 free c standard file C

free c standard file C
https://www.eeworm.com/dl/684/387857.html
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软件设计/软件工程 free c++ standard file Cpp2003

free c++ standard file Cpp2003
https://www.eeworm.com/dl/684/387859.html
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数学计算 FDTD code in Free Space with no absorbing boundary conditions.

FDTD code in Free Space with no absorbing boundary conditions.
https://www.eeworm.com/dl/641/387968.html
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matlab例程 Absorbing Boundary Conditions in Free Space

Absorbing Boundary Conditions in Free Space
https://www.eeworm.com/dl/665/387969.html
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matlab例程 ABC_FDTD_Die(T) Implements simulation of a Gaussian Pulse over T time steps. ABC are for free spac

ABC_FDTD_Die(T) Implements simulation of a Gaussian Pulse over T time steps. ABC are for free space. If boundaries are in the Dielectric medium then the ABC fail. Dielectric medium begin and end can be specified with the code
https://www.eeworm.com/dl/665/387970.html
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matlab例程 ABC_FDTD_Die(T) Implements simulation of a Gaussian Pulse over T time steps. ABC are for free spac

ABC_FDTD_Die(T) Implements simulation of a Gaussian Pulse over T time steps. ABC are for free space. If boundaries are in the Dielectric medium then the ABC fail. Dielectric medium begin and end can be specified with the code
https://www.eeworm.com/dl/665/387971.html
下载: 132
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VHDL/FPGA/Verilog This a FREE tool chain which compiles C codes into 8051 binary code, converts the binary to RTL ROM,

This a FREE tool chain which compiles C codes into 8051 binary code, converts the binary to RTL ROM, and simulate in Modelsim. SDCC is the compiler. Example compilation: cd compile sdcc --iram-size 0x80 --xram-size 0x800 t8051.c REM sdcc --iram-size 0x80 t8051.c packihx t8051.ihx > t8051.hex ...
https://www.eeworm.com/dl/663/389049.html
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