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通讯编程文档 This paper will discuss the design of an asynchronous FIFO,Asynchronous FIFOs are widely used in the
This paper will discuss the design of an asynchronous FIFO,Asynchronous FIFOs are widely used in the computer networking industry to receive data at
a particular frequency and transmit them at another frequency. An asynchronous FIFO has
two different clocks: one for read and one for write.
通信网络 XAPP807-封装最小的三态以太网MAC处理引擎
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an exte ...
其他 The first task at hand is to set up the endpoints appropriately for this example. The following code
The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed
to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6
as a Bulk IN endpoint, also 4x buffered of si ...
VHDL/FPGA/Verilog Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation.
As with the SPI found in MC68HC11 processo ...
VHDL/FPGA/Verilog 这个设计是使用Virtex-4实现DDR的控制器的
这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。
操作系统开发 A badic controller for the UART. It incorporates a -- transmit and receive FIFO (fr
A badic controller for the UART. It incorporates a
-- transmit and receive FIFO (from Max+Plus II s MegaWizard
-- plug-in manager). Note that no checking is done to see
-- whether the FIFOs are overflowing or not. This strictly
-- handle ...