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VHDL/FPGA/Verilog Altera provides a number of reference designs that show efficient solutions for common design proble
Altera provides a number of reference designs that show efficient solutions for common design problems. Altera&#174 reference designs can be used to develop new solutions and innovative products, improve your understanding of Altera product capabilities, as well as help reduce your design time. The ...
通讯/手机编程 master interleaver with aks design..its a matlab code program.
master interleaver with aks design..its a matlab code program.
编辑器/阅读器 operating system internal and Design principles 5th
operating system internal and Design
principles 5th
VHDL/FPGA/Verilog Clock based on the VHDL design language, the revised time alarm can be set up
Clock based on the VHDL design language, the revised time alarm can be set up
游戏 Here is a ActiveX User Control to design a Calculator, and also a library file to access Windows Reg
Here is a ActiveX User Control to design a Calculator, and also a library file to access Windows Registry and settings files, This download is only for Visual Basic 6 developers.
软件设计/软件工程 threading basics, design principles
threading basics, design principles
软件设计/软件工程 Video Game Design and Development
Video Game Design and Development
嵌入式Linux Analysis of GPS data frame The design of the following four main data collection format: GPGGA (loc
Analysis of GPS data frame
The design of the following four main data collection format: GPGGA (location information), GPRMC (Recommended Minimum location information), GPVTG (ground speed information), PGRME (forecast error message)
系统设计方案 PXA270 design guide low level primitives
PXA270 design guide low level primitives
无线通信 RF Amplifier Design
RF Amplifier Design：1. Active devices and S-parameters
2. Amplifier impedance matching technique
3. Power gain of amplifiers
4. Stability of RF amplifiers
5. Power gain circles of amplifiers
6. Bias networks of active devices
7. Small signal amplifier design example