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可编程逻辑 XAPP806 -决定DDR反馈时钟的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microproces ...
https://www.eeworm.com/dl/kbcluoji/40078.html
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可编程逻辑 XAPP328-使用CPLD设计MP3播放器

  MP3 portable players are the trend in music-listening technology. These players do not includeany mechanical movements, thereby making them ideal for listening to music during any type ofactivity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music ina lot less ...
https://www.eeworm.com/dl/kbcluoji/40098.html
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可编程逻辑 XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥

  The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Spec ...
https://www.eeworm.com/dl/kbcluoji/40099.html
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可编程逻辑 Verilog编码中的非阻塞性赋值

  One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...
https://www.eeworm.com/dl/kbcluoji/40125.html
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可编程逻辑 CPLD和FPGA设计介绍

Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system ...
https://www.eeworm.com/dl/kbcluoji/40148.html
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可编程逻辑 allegro cx manual教程

We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi  eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegr ...
https://www.eeworm.com/dl/kbcluoji/40217.html
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可编程逻辑 基于FPGA的光纤光栅解调系统的研究

 波长信号的解调是实现光纤光栅传感网络的关键,基于现有的光纤光栅传感器解调方法,提出一种基于FPGA的双匹配光纤光栅解调方法,此系统是一种高速率、高精度、低成本的解调系统,并且通过引入双匹配光栅有效地克服了双值问题同时扩大了检测范围。分析了光纤光栅的测温原理并给出了该方案软硬件设计,综合考虑系统的解 ...
https://www.eeworm.com/dl/kbcluoji/40240.html
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可编程逻辑 UART 4 UART参考设计,Xilinx提供VHDL代码

UART 4 UART参考设计,Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders:  \vhdl_source  -- Source VHDL files:      uart.vhd  - top level file      txmit.vhd - transmit portion of uart  &nb ...
https://www.eeworm.com/dl/kbcluoji/40395.html
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可编程逻辑 pci e PCB设计规范

This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on b ...
https://www.eeworm.com/dl/kbcluoji/40445.html
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测试测量 RSM-7404 计数测频数据采集模块产品数据手册

RSM是广州致远电子有限公司全新系列的基于RS-485接口的数据采集模块。RSM数据采集模块在单个设备中集成了I/O、数据采集和隔离的RS-485总线接口。支持标准的Modbus协议和自定义ASCII协议。RSM-7404是计数/测频模块,具有4路32位计数/测频通道,其中包括2路隔离通道和2路非隔离通道,以满足不同场合需求;模块还具有4路的DO通 ...
https://www.eeworm.com/dl/544/41923.html
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