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matlab例程 实现产生伪随机序列的部件 —— 线性反馈移位寄存器单元。 SFlog2为扩频因子的底数为2的对数值
实现产生伪随机序列的部件 —— 线性反馈移位寄存器单元。 SFlog2为扩频因子的底数为2的对数值，cycle为PN序列的周期，其值为2^SFlog2。initial_state为移位寄存器的初始状态，generator_polynomial_coefficient为生成PN序列所需的本原多项式，对应于移位寄存器的连接向量。 ...
软件设计/软件工程 The purpose of this document is to present how to use the Timer for the generation of a PWM signal t
The purpose of this document is to present how to use the Timer for the generation of a PWM signal tunable in frequency and duty cycle. As an application example, this document is based on a basic “music” synthesizer through an external buzzer. Example code is also available in the it.
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
DSP编程 完成在tigersharc201平台上划分出多个heap的操作
完成在tigersharc201平台上划分出多个heap的操作，同时示例在多个heap之间切换时的方法，并做出各种内存下访问的cycle统计
汇编语言 *** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 2
*** *** *** *** *** *** *****
** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s
** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a
** PIC16C54 8-bit CMOS single chip microcomputer
** Revsied Version 2.0 (4/2/92).
**
** Part use = PIC16C54-XT/JW
** Note: 1) All timings are base ...
VHDL/FPGA/Verilog It contains a vhdl description of the external bus interface unit for 68000 processor. currently onl
It contains a vhdl description of the external bus interface unit for 68000 processor. currently only read and write cycle are supported
其他 Edge Disjoint Cycles. You are given an input graph that is either directed or undirected. Write a pr
Edge Disjoint Cycles. You are given an input graph that is either directed or undirected. Write a program that reads in a vertex number and lists the number of edge disjoint cycles that start and end at this vertex. The output should also list the edges in each of the cycle discovered. Input will be ...
数值算法/人工智能 蚁群算法经典TSP模型
蚁群算法经典TSP模型，ANT-CYCLE算法的实现。
使用了C++的STL库。
原是我毕设的一部分 现在贡献出来 。
PS:网上能得到的基本上不能直接运行
而我这个复制到vc++6.0的控制台工程中即可
文件中的文件“oliver30Tsp.dat”
为实现蚁群算法的经典例子，网上还有很多类似的测试例子 ...
DSP编程 This experiment uses the Blackfi n BF533/BF537 EZ-KIT to run a simple FIR fi lter on stereo channe
This experiment uses the Blackfi n BF533/BF537 EZ-KIT to run a simple FIR fi lter on stereo
channels at a sampling frequency of 48 kHz. The
CYCLE register is embedded in the main
program (
process_data.c) to benchmark the time needed to process two FIR fi lters. A
background telemetry channel (B ...