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教程资料 8259 VHDL代码
a8259 可编程中断控制 altera提供
The a8259 is designed to simplify the implementation of the interrupt interface  in 8088 and 8086  based microcomputer systems. The device is known as a programmable interrupt controller.  The a8259 receives and prioritizes up to 8 interrupts,  ...
通信网络 XAPP807-封装最小的三态以太网MAC处理引擎
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an exte ...
嵌入式综合 lpc2292/lpc2294 pdf datasheet
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum ...
ARM LPC314x系列ARM微控制器用户手册
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication mark ...
ARM LPC315x系列ARM微控制器用户手册
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, in ...
C/C++语言编程 飞思卡尔智能车的舵机测试程序
飞思卡尔智能车的舵机测试程序
#include <hidef.h>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* common defines and macros */#include <MC9S12XS128.h>&nbsp;&nbsp;&nbsp;&nbsp; /* derivative information */#pragma LINK_INFO DERIVATIVE "mc9s12xs128"
void SetBusCLK_16M(void)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp ...
C/C++语言编程 基于（英蓓特）STM32V100的串口程序
This example provides a description of how&nbsp; to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypa ...
可编程逻辑 Xilinx UltraScale：新一代架构满足您的新一代架构需求（EN）
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx&reg; UltraScale&trade; architecture delivers unprecedented levels of integration and capability with ASIC-class ...
可编程逻辑 XAPP806 -决定DDR反馈时钟的最佳DCM相移
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microproces ...
可编程逻辑 XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥
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The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Spec ...