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可编程逻辑  XAPP098 - Spartan FPGA低成本、高效率串行配置

This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration ci ...

https://www.eeworm.com/dl/kbcluoji/40059.html

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可编程逻辑  XAPP444 - CPLD配件,技巧和窍门

Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determ ...

https://www.eeworm.com/dl/kbcluoji/40063.html

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可编程逻辑  XAPP380 -利用CoolRunner-II CPLD创建交叉点开关

&nbsp; This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner&trade;-II CPLD device but can be easily expanded to target higherdensit ...

https://www.eeworm.com/dl/kbcluoji/40074.html

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可编程逻辑  Virtex-6 FPGA PCB设计手册

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in ...

https://www.eeworm.com/dl/kbcluoji/40076.html

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可编程逻辑  WP264-在数字视频应用中使用CPLD

&nbsp; The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blo ...

https://www.eeworm.com/dl/kbcluoji/40077.html

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可编程逻辑  XAPP806 -决定DDR反馈时钟的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microproces ...

https://www.eeworm.com/dl/kbcluoji/40078.html

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可编程逻辑  XAPP953-二维列序滤波器的实现

&nbsp; This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horiz ...

https://www.eeworm.com/dl/kbcluoji/40089.html

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可编程逻辑  XAPP944 - 将Xilinx CoolRunner-II CPLD用作数据流开关

&nbsp; This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the &ldquo;VHDLCode&rdquo; se ...

https://www.eeworm.com/dl/kbcluoji/40092.html

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可编程逻辑  XAPP390 - 利用CoolRunner-II CPLD设计数码相机

&nbsp; Digital cameras have become increasingly popular over the last few years. Digital imagingtechnology has grown to new markets including cellular phones and PDA devices. With thediverse marketplace, a variety of imaging technology must be available. Imaging technologyhas expanded to include ...

https://www.eeworm.com/dl/kbcluoji/40095.html

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可编程逻辑  XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器

&nbsp; Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan&reg;-6 FPGAs togenerate spread-spectrum ...

https://www.eeworm.com/dl/kbcluoji/40096.html

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