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教程资料  Analog Solutions for Xilinx FPGAs

Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calle ...

https://www.eeworm.com/dl/fpga/doc/32538.html

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教程资料  Analog Solutions for Altera FPGAs

Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells calle ...

https://www.eeworm.com/dl/fpga/doc/32541.html

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教程资料  wp379 AXI4即插即用IP

In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting ch ...

https://www.eeworm.com/dl/fpga/doc/32564.html

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教程资料  XAPP694-从配置PROM读取用户数据

This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in t ...

https://www.eeworm.com/dl/fpga/doc/32574.html

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教程资料  XAPP452-Spartan-3高级配置架构

This application note provides a detailed description of the Spartan&trade;-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide th ...

https://www.eeworm.com/dl/fpga/doc/32580.html

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教程资料  XAPP228 -Virtex器件内的四端口存储器

This application note describes how the existing dual-port block memories in the Spartan&trade;-IIand Virtex&trade; families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in ...

https://www.eeworm.com/dl/fpga/doc/32585.html

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教程资料  XAPP098 - Spartan FPGA低成本、高效率串行配置

This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration ci ...

https://www.eeworm.com/dl/fpga/doc/32590.html

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教程资料  Virtex-6 FPGA PCB设计手册

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in ...

https://www.eeworm.com/dl/fpga/doc/32592.html

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教程资料  XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器

&nbsp; Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan&reg;-6 FPGAs togenerate spread-spectrum ...

https://www.eeworm.com/dl/fpga/doc/32595.html

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教程资料  XAPP806 -决定DDR反馈时钟的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microproces ...

https://www.eeworm.com/dl/fpga/doc/32600.html

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