搜索结果
找到约 71 项符合
Asynchronous 的查询结果
按分类筛选
- 全部分类
- VHDL/FPGA/Verilog (11)
- 单片机编程 (6)
- 行业发展研究 (5)
- matlab例程 (4)
- 学术论文 (3)
- 其他书籍 (3)
- 其他嵌入式/单片机内容 (3)
- 加密解密 (3)
- 通讯编程文档 (3)
- 教程资料 (2)
- Java编程 (2)
- Java书籍 (2)
- 单片机开发 (2)
- 其他 (2)
- Ajax (2)
- 系统设计方案 (2)
- 技术资料 (2)
- 其他文档 (1)
- 电机控制 (1)
- 模拟电子 (1)
- 可编程逻辑 (1)
- 工控技术 (1)
- Internet/网络编程 (1)
- SQL Server (1)
- 技术管理 (1)
- 汇编语言 (1)
- USB编程 (1)
- 文件格式 (1)
- 文章/文档 (1)
- 邮电通讯系统 (1)
- DSP编程 (1)
其他 Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availabilit
Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availability of four serial ports: double synchronous serial ports (I&sup2 C&#8482 and SPI&#8482 ) and double asynchronous (LIN capable) serial ports. Large amounts of RAM memory for buffering and FLASH program ...
其他书籍 本人收集的ajax一些资料
本人收集的ajax一些资料，打印版。
Ajax这个概念的最早提出者Jesse James Garrett认为：
Ajax是Asynchronous JavaScript and XML的缩写。
Ajax并不是一门新的语言或技术,它实际上是几项技术按一定的方式组合在一在同共的协作中发挥各自的作用,它包括
使用XHTML和CSS标准化呈现
使用DOM实现动态显示和交互 ...
加密解密 A Linux port of the OpenBSD/FreeBSD Cryptographic Framework (OCF). This port aims to bring full asyn
A Linux port of the OpenBSD/FreeBSD Cryptographic Framework (OCF). This port aims to bring full asynchronous HW/SW crypto acceleration to the Linux kernel, OpenSwan, OpenSSL and applications using DES, 3DES, AES, MD5, SHA, PublicKey, RNGs and more.
VHDL/FPGA/Verilog vhdl编写
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
...
加密解密 CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 b
CRC码产生器与校验器程序
Features ：
Executes in one clock cycle per data word
Any polynomial from 4 to 32 bits
Any data width from 1 to 256 bits
Any initialization value
Synchronous or asynchronous reset
Ajax 基于AJAX的动态树型结构的设计与实现 简要介绍了一种通用的
基于AJAX的动态树型结构的设计与实现
简要介绍了一种通用的，动态树型结构的实现方案，该方案基于Asynchronous JavaScript and XML，结合Struts框架设计实现了结构清晰、扩展性良好的多层架构，数据存储于数据库，结合XML描述树的节点信息，使得任何按预定的XML文档描述的信息都可以通过动态树来展现。 ...
VHDL/FPGA/Verilog Serial UART open source core. The design is engineered for use as a stand alone chip or for use with
Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we nee ...
行业发展研究 The use of hardware description languages (HDLs) is becoming increasingly common for designing and
The use of hardware description languages (HDLs) is becoming
increasingly common for designing and verifying FPGA designs.
Behavior level description not only increases design productivity, but also
provides unique advantages for design verification. The most dominant
HDLs today are Verilog and VHDL ...
VHDL/FPGA/Verilog The objective of this project is to create a driver for a camera module (we used the OV7620). After
The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable
技术资料 基于TMS320F28035芯片为控制核心的空间矢量异步电机变频器
基于TMS320F28035芯片为控制核心的空间矢量异步电机变频器  我们设计的异步电机变频调速器以TMS320F28035芯片为控制核心，通过输出三相PWM波控制智能功率模块IPM驱动三相异步电机。我们使用空间矢量SVPWM算法，并对其进行了优化。采用检测反电势的方法省去了昂贵的光电编码器，大大节省了成本。同时开创性的研发了自动 ...