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可编程逻辑  Nios II定制指令用户指南

&nbsp;&nbsp;&nbsp;&nbsp; Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequen ...

https://www.eeworm.com/dl/kbcluoji/39394.html

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可编程逻辑  ALTERA的FPGA_的AS、PS和Jtag配置模式区别

altera

https://www.eeworm.com/dl/kbcluoji/39618.html

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可编程逻辑  Employing a Single-Chip Transceiver in Femtocell Base-Station Applications

Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective s ...

https://www.eeworm.com/dl/kbcluoji/39952.html

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可编程逻辑  wp379 AXI4即插即用IP

In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting ch ...

https://www.eeworm.com/dl/kbcluoji/40023.html

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可编程逻辑  XAPP503-针对Xilinx器件的SVF和XSVF文件格式

This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded pro ...

https://www.eeworm.com/dl/kbcluoji/40051.html

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可编程逻辑  XAPP228 -Virtex器件内的四端口存储器

This application note describes how the existing dual-port block memories in the Spartan&trade;-IIand Virtex&trade; families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in ...

https://www.eeworm.com/dl/kbcluoji/40055.html

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可编程逻辑  XAPP098 - Spartan FPGA低成本、高效率串行配置

This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration ci ...

https://www.eeworm.com/dl/kbcluoji/40059.html

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可编程逻辑  XAPP444 - CPLD配件,技巧和窍门

Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determ ...

https://www.eeworm.com/dl/kbcluoji/40063.html

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可编程逻辑  XAPP440 - Xilinx CPLD的上电性能

Applying power to a standard logic chip, SRAM, or EPROM, usually results in output pinstracking the applied voltage as it rises. Programmable logic attempts to emulate that behavior,but physics forbids perfect emulation, due to the device programmability. It requires care tospecify the pin behavio ...

https://www.eeworm.com/dl/kbcluoji/40065.html

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可编程逻辑  XAPP144 -设计CPLD多电压系统

Today&rsquo;s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories&mdash;both RAM and ROM&mdash;as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for han ...

https://www.eeworm.com/dl/kbcluoji/40067.html

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