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人工智能/神经网络 Chi Square Test for Independence: calculuate the chi square of a vector and the critical value.
Chi Square Test for Independence: calculuate the chi square of a vector and the critical value.
数学计算 A toolbox to handle 2D curve and multiresolution representation of curve
A toolbox to handle 2D curve and multiresolution representation of curve
人工智能/神经网络 If we have two individually sorted vectors "a" and "b" but they are not sorted with respect to each
If we have two individually sorted vectors "a" and "b" but they are not sorted with respect to each other and we want to merge them into vector "c" such that "c" is also a sorted vector. Then c=mergesorted(a,b) can be used.
数学计算 Two functions, num2bin and bin2num are provided. num2bin takes a double and converts it to a binary
Two functions, num2bin and bin2num are provided. num2bin takes a double and converts it to a binary string representation. bin2num is its inverse operation. It can be used in a numerical analysis course when floating point arithmetic is discussed.
Java编程 One-channel queuing system simulator (M/M/1) * Arrival and service times are random and distributed
One-channel queuing system simulator (M/M/1)
* Arrival and service times are random and distributed exponetially.
*
* The simulator is time-slice-driven, i.e. the system model is being
* run at discrete time points, with constant increments deltaT.
* At each such time moment, program checks if a n ...
数学计算 fft and convolution
fft and convolution
人工智能/神经网络 Simulated Annealing for both Stochastic models and Deterministic models
Simulated Annealing for both Stochastic models and Deterministic models
单片机开发 This a two node test, requires a Coordinator and an RFD. The coordinator and node simply ping-pong
This a two node test, requires a Coordinator
and an RFD. The coordinator and node simply
ping-pong a packet back and forth, and print
out the RSSI byte. The RFD waits before
bouncing it back, while the coordinator responds
immediately.
其他书籍 Verilog and VHDL状态机设计
Verilog and VHDL状态机设计,英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a var ...
行业发展研究 I believe that technology has the capacity to fundamentally improve people’s lives, and improve the
I believe that technology has the capacity to fundamentally improve people’s lives, and
improve the world in which we live.We are now two years into what my company have
called the ‘Digital Decade’.We think that by 2010 a combination of hardware and software
innovation with broader social trends ...