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VHDL/FPGA/Verilog 通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit
通用寄存器的部分代码
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY traffic IS
PORT(clk,sm,sb:IN bit
mr,my,mg,br,by,bg:OUT bit
)
END traffic
VHDL/FPGA/Verilog Using Hierarchy in VHDL Design vhdl语言初学者的天堂
Using Hierarchy in VHDL Design
vhdl语言初学者的天堂
Java书籍 javaexample in nutshell 第三版全书源码
javaexample in nutshell 第三版全书源码
其他 when detect the bit meet, then set th bit in bit map
when detect the bit meet, then set th bit in bit map
其他 dm s preparing process. In this case we use O distance.
dm s preparing process. In this case we use O distance.
串口编程 模拟串口的程序:Generic software uart written in C
模拟串口的程序:Generic software uart written in C
生物技术 The software package provides a MAX-MIN Ant System implemented in the Hyper-Cube Framework for the
The software package provides a MAX-MIN Ant System implemented in the
Hyper-Cube Framework for the application to Unconstrained Binary Quadratic
Programming (UBQP).
其他书籍 Using short message service to encourage interactivity in the classroom.rar
Using short message service to encourage interactivity in the classroom.rar
其他 -PID controller has been extensively used in the industrial world. But in this controller it is dif
-PID controller has been extensively
used in the industrial world. But in this controller it is difficult to tune the PID gains.
We apply the genetic algorithm(GA) to tune the PID gains. The GA is an optimization algorithm using the biotic genetics.
matlab例程 This a very simple Yee algorithm 3D FDTD code in C implementing the free space form of Maxwell s equ
This a very simple Yee algorithm 3D FDTD code in C implementing the free space form of Maxwell s equations on a Cartesian grid. There are no internal materials or geometry. The code as delivered simulates an idealized rectangular waveguide by treating the interior of the mesh as free space/air and e ...