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VHDL/FPGA/Verilog Serial UART open source core. The design is engineered for use as a stand alone chip or for use with
Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we nee ...
单片机开发 extral flash control by SPI, as possible as you can ,very good
extral flash control by SPI, as possible as you can ,very good
游戏 ssd4ex6 vb 6.0 Aplications that emules the date&time interface of windows xp or below.
ssd4ex6
vb 6.0 Aplications that emules the date&time interface of windows xp or below.
VHDL/FPGA/Verilog It contains a vhdl description of the external bus interface unit for 68000 processor. currently onl
It contains a vhdl description of the external bus interface unit for 68000 processor. currently only read and write cycle are supported
uCOS This Program Cotains Eeprom Read-write functions, 4 Bit LCD interface routines, Keyboard Interface w
This Program Cotains Eeprom Read-write functions, 4 Bit LCD interface routines, Keyboard Interface with normal Key Input to the 89C52 atmel Microcontroller.
其他 gps interface code that using visual basic code. This basically separate the NMEA code
gps interface code that using visual basic code. This basically separate the NMEA code
Java书籍 Java Card™ 2.2 Application Programming Interface
Java Card™ 2.2
Application Programming Interface
软件设计/软件工程 Java native interface Documentation
Java native interface Documentation
Delphi/CppBuilder 易飞ERP二次开发接口制作完成 Yi-fei ERP finished secondary development interface
易飞ERP二次开发接口制作完成
Yi-fei ERP finished secondary development interface
系统设计方案 等精度频率计的毕业设计论文 是通过学校严格审查通过的Such as the accuracy of the frequency of graduate design thesis
等精度频率计的毕业设计论文 是通过学校严格审查通过的Such as the accuracy of the frequency of graduate design thesis