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人工智能/神经网络 Locally weighted polynomial regression LWPR is a popular instance based al gorithm for learning c
Locally weighted polynomial regression LWPR is a popular instance based al gorithm for learning continuous non linear mappings For more than two or three in puts and for more than a few thousand dat apoints the computational expense of pre dictions is daunting We discuss drawbacks with previous ...
其他 apriori java 实现 * A program to find association rules with the apriori algorithm (Agrawal et al. 199
apriori java 实现 * A program to find association rules with the apriori algorithm (Agrawal et al. 1993).<br> * Other than the standard apriori algorithm, this program enable to find<br> * apriori all relation.
人工智能/神经网络 this program, opticalflow.c, is an implementation of Uras et al. 1988 s motion
this program, opticalflow.c, is an implementation of Uras et al. 1988 s motion
Internet/网络编程 作者:【美】Al Williams中国水利水电出版社 包含Telnet、FTP、TFTP、SMTP、POP3等协议网络设计的代码
作者:【美】Al Williams中国水利水电出版社
包含Telnet、FTP、TFTP、SMTP、POP3等协议网络设计的代码
驱动编程 鼎铭在线al-100tx网卡驱动程序(xp不自驱
鼎铭在线al-100tx网卡驱动程序(xp不自驱,网上独此一份)
matlab例程 Recent work by Petricoin and Liotta and co-workers (Petricoin et al. Use of proteomic patterns in se
Recent work by Petricoin and Liotta and co-workers (Petricoin et al. Use of proteomic patterns in serum to identify ovarian cancer. Lancet. 2002 Feb 16 359(9306):572-7. PMID: 11867112) has generated a lot of excitement and controversy. This example shows some ways that MATLAB can be used to read, vi ...
嵌入式/单片机编程 altera pci license al tera pci license
altera pci license al tera pci license
RFID编程 RFID Security - F. Thornton, B. Haines, A. Das, et al - Syngress - 2006
RFID Security - F. Thornton, B. Haines, A. Das, et al - Syngress - 2006
Delphi/CppBuilder Bascula conectada al puerto serie
Bascula conectada al puerto serie
VHDL/FPGA/Verilog Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci
Stereo-Vision circuit description, Aug 2002,
Ahmad Darabiha
This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and
sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the
sub-circuits can be used as smaller benchmarks.