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系统设计方案 This application note describes a method for developing block-oriented I/O device drivers for appli
This application note describes a method for developing block-oriented I/O device drivers
for applications that use the DSP/BIOS real-time kernel and includes examples that run
with Code Composer Studio v2.1 on the Texas Instruments TMS320C5402 and
TMS320C6711 DSP Starter Kits (DSKs). The device dri ...
数学计算 函数模板T max(T a, T b, T c),使之实现对任何类型数
函数模板T max(T a, T b, T c),使之实现对任何类型数，能从三个数中求出最大数返回。设计各种类型数据(char，short，long，float，double)调用此函数模板。
Java书籍 Spring: A Developer s Notebook 一本关于介绍Spring的好书
Spring: A Developer s Notebook
一本关于介绍Spring的好书，2005年出版
VHDL/FPGA/Verilog A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx
A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx
电子书籍 This a set of notes I put together for my Computer Architecture class in 1990. Students had a proje
This a set of notes I put together for my Computer Architecture
class in 1990. Students had a project in which they had to model a
microprocessor architecture of their choice. They used these notes to
learn VHDL. The notes cover the VHDL-87 version of the language.
Not all of the language is covere ...
电子书籍 modelsim_se_tutorThis is a set of notes I put together for my Computer Architecture class in 1990.
modelsim_se_tutorThis is a set of notes I put together for my Computer Architecture
class in 1990. Students had a project in which they had to model a
microprocessor architecture of their choice. They used these notes to
learn VHDL. The notes cover the VHDL-87 version of the language.
Not all of th ...
电子书籍 This is a set of notes I put together for my Computer Architecture class in 1990. Students had a pr
This is a set of notes I put together for my Computer Architecture
class in 1990. Students had a project in which they had to model a
microprocessor architecture of their choice. They used these notes to
learn VHDL. The notes cover the VHDL-87 version of the language.
Not all of the language is cov ...
VHDL/FPGA/Verilog This build is for developing a "binary-to-BCD" converter for use in // displaying numerals in base-
This build is for developing a "binary-to-BCD" converter for use in
// displaying numerals in base-10 so that people can read and interpret the
// numbers more readily than they could if the numbers were displayed in
// binary or hexadecimal format. Also, a "BCD-to-binary" converter is
// tested in ...
VHDL/FPGA/Verilog IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at
IDCT-M is a medium speed 1D IDCT core
-- it can accept a continous stream of 12-bit input words at a rate of
-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video
-- the core is 100％ synthesizable
VHDL/FPGA/Verilog BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chi
BurchED B5-X300 Spartan2e
using XC2S300e device
Top level file for 6809 compatible system on a chip
Designed with Xilinx XC2S300e Spartan 2+ FPGA.
Implemented With BurchED B5-X300 FPGA board,
B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module