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数学计算 This file implements a pid controller used to simulator cruise control in a car The input is a thr
This file implements a pid controller used to simulator cruise control in a car
The input is a throtle value between 0 - 100 ( read on P1 )
The output is the car s speed ( P2 - P0 )
汇编语言 数字电压表 AD芯片： 采用8位串行A/D转换器ADC0832。 ● 8位分辨率
数字电压表
AD芯片：
采用8位串行A/D转换器ADC0832。
● 8位分辨率，逐次逼近型，基准电压为 5V
● 5V单电源供电
● 输入模拟信号电压范围为 0～5V
● 有两个可供选择的模拟输入通道
汇编语言 伟福LAB2000单片机仿真系统直流电机控制:利用实验仪上的D/A变换电路
伟福LAB2000单片机仿真系统直流电机控制:利用实验仪上的D/A变换电路，输出-8V至+8V电压，控制直流电机。改变输出电.压值，改变电机转速，用8255 的PB.0 读回脉冲计数，计算电机转速。在电压允许范围内，直流电机的转速随着电压的升高而加快，若加上的电压为负电压，则电机会反向旋转。本实验仪的D/A变换可输出-8V到+8V的电 ...
matlab例程 外国人开发的电磁时域有限差分方法工具包 Electromagnetic Finite-Difference Time-Domain (EmFDTD) is a basic two-dimensio
外国人开发的电磁时域有限差分方法工具包
Electromagnetic Finite-Difference Time-Domain (EmFDTD)
is a basic two-dimensional FDTD code developed at the
School of Electrical Engineering, Sharif University of
Technology.
This code has been written based on the standard
Yee s FDTD algorithm. Applicati ...
数学计算 采用NLJ随机搜索的方法辨识一个以状态方法表示的非线性系统。选其初值 a1(0) =50 , a2(0) =100 , a3(0) =100 , a4(0) =50 , a5(0) =10 , 选范围
采用NLJ随机搜索的方法辨识一个以状态方法表示的非线性系统。选其初值 a1(0) =50 , a2(0) =100 , a3(0) =100 , a4(0) =50 , a5(0) =10 , 选范围为 r(1)(i)=0.5 a(0)(i) , 取数据长度 L ＝40, t =0.005 , 性能指标 J＝ 。迭代计算结果得 a 的估计值 1=17.6043243, 1=17.5977, 2=72.9573, 3=51.3014, 4=22.9889, 5=5.99965, J ...
Java编程 Thinking in Java, 3rd ed. Revision 4.0 Preface Introduction 1: Introduction to Objects 2
Thinking in Java, 3rd ed. Revision 4.0
Preface
Introduction
1: Introduction to Objects
2: Everything is an Object
3: Controlling Program Flow
4: Initialization & Cleanup
5: Hiding the Implementation
6: Reusing Classes
7: Polymorphism
8: Interfaces & Inner Classes
9: Error Handling with Ex ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
VHDL/FPGA/Verilog Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
数学计算 用盛金公式解一元三次方程aX3＋bX2＋cX＋d=0
用盛金公式解一元三次方程aX3＋bX2＋cX＋d=0，（a，b，c，d∈R，且a≠0）。